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1. Introduction to the Intel® Agilex™ Device Design Guidelines
2. System Specification
3. Device Selection
4. Security Considerations
5. Design Entry
6. Board and Software Considerations
7. Design Implementation, Analysis, Optimization, and Verification
8. Debugging
9. Embedded Software Design Guidelines for Intel® Agilex™ SoC FPGAs
5.1.1. Firewall Planning
5.1.2. Boot And Configuration Considerations
5.1.3. HPS Clocking and Reset Design Considerations
5.1.4. Reset Configuration
5.1.5. HPS Pin Multiplexing Design Considerations
5.1.6. HPS I/O Settings: Constraints and Drive Strengths
5.1.7. Design Guidelines for HPS Interfaces
5.1.8. Interfacing between the FPGA and HPS
5.1.9. Implementing the Intel® Agilex™ HPS Component
7.1. Selecting a Synthesis Tool
7.2. Device Resource Utilization Reports
7.3. Intel® Quartus® Prime Messages
7.4. Timing Constraints and Analysis
7.5. Area and Timing Optimization
7.6. Preserving Performance and Reducing Compilation Time
7.7. Designing with Intel® Hyperflex™
7.8. Simulation
7.9. Power Analysis
7.10. Power Optimization
7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
9.1. Overview
9.2. Golden Hardware Reference Design (GHRD)
9.3. Define Software Requirements
9.4. Define Software Architecture
9.5. Selecting Software Tools
9.6. Choosing the Bootloader Software
9.7. Selecting an Operating System for Your Application
9.8. Assembling Your Software Development Platform for Linux*
9.9. Assembling your Software Development Platform for Partner OS or RTOS
9.10. Driver Considerations
9.11. Boot And Configuration Considerations
9.12. System Reset Considerations
9.13. Flash Considerations
9.14. Develop Application
9.15. Test and Validate
9.16. Embedded Software Design Guidelines Revision History
9.13.1. Flash Programming Method
GUIDELINE: Use Intel® Quartus® Prime Pro Edition Programmer to write to SDM flash.
GUIDELINE: Plan for the HPS flash programming method early in the project lifecycle, as it may impact board design or require additional tool support.
9.13.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage
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9.13.1. Flash Programming Method
The flash connected to SDM is programmed using the Intel® Quartus® Prime Programmer tool, that is part of both Intel® Quartus® Prime Pro Edition and Intel® SoC FPGA Embedded Development Suite (SoC EDS).
GUIDELINE: Use Intel® Quartus® Prime Pro Edition Programmer to write to SDM flash.
It is your responsibility to program the flash connected to HPS. Several options are possible:
- Use a bus switch to route the flash signals to an external master that does the programming.
- Use software running on HPS to do the programming. For example U-Boot can be loaded with an Arm* debugger or System Console, then used to program the flash.