AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

5.3.2.3. HPS Memory Debug

GUIDELINE: Verify the memory interface is operational using an FPGA EMIF and the external memory tool kit.

Because the HPS EMIF controller does not support the external memory interface toolkit, verify that the memory interface is operational using the non-HPS memory controller first. Create a design that instantiates the FPGA memory controller and routes it to the same I/O that the HPS EMIF uses.

For more information, refer to the following documentation:
  • Intel® Agilex™ External Memory Interface Pin Information
  • Intel® Agilex™ FPGA External Memory Interface Overview

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