AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

7.7. Designing with Intel® Hyperflex™

Table 95.  Designing with Intel® Hyperflex™ Checklist
Number Done? Checklist Item
1   Use Intel® Hyperflex™ feature to optimize your design and achieve enhanced performance.

Intel® Hyperflex™ core architecture adds registers to both the interconnect routing and the inputs of all major functional blocks in the FPGA. These added registers, called Hyper-Registers, are different from conventional registers. Conventional registers are present only in the adaptive logic modules (ALMs). Hyper-Registers can help to achieve significant core performance improvement.

To achieve this enhanced performance, you must optimize your designs using the following steps:
  1. Hyper-Retiming
  2. Hyper-Pipelining
  3. Hyper-Optimization

For more information about high performance design, refer to the Intel® FPGA Technical Training website.

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