AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022

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5.7. Design Entry Revision History

Table 48.  Design Entry Revision History
Document Version Changes
2022.08.26 Corrected the link to the Golden Hardware Reference Design (GHRD) section
  • Changed "HPS Cold reset and trigger a remote Update" to "Trigger Remote Update" in the System Reset Considerations section.
  • Added information about F-Tile to the Transceiver Planning section.
  • Added a link to point to the FPGA-to-HPS Restrictions section of the Intel® Agilex™ Hard Processor System Technical Reference Manual.
  • Renamed the FPGA-to-SoC and SoC-to-FPGA bridges to FPGA-to-HPS and HPS-to-FPGA.
  • Added information about F-Tile and R-Tile to the Transceiver Planning section.
2020.09.15 Removed the Engineering Sample Device Restrictions Guideline from the Selecting HPS Boot Options section.
2020.06.22 Updated the Overview of HPS Memory-Mapped Interfaces with guidelines for protection methodology and its expectation and solutions.
2019.09.30 Initial release