AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022

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Document Table of Contents

5.3.2. HPS EMIF Design Considerations

A critical component to the HPS is its external SDRAM memory. The following design considerations help you properly design the interface between SDRAM memory and the HPS.

When connecting external SDRAM to the HPS, refer to the following EMIF planning tools and essential documentation:

EMIF Planning Tools

Tools Description
External Memory Interfaces IP - Support Center The External Memory Interfaces IP - Support Center is a collection of tools and documentation resources to aid in the design of external memory interfaces for Intel® FPGAs.

For more information about EMIF IP generation and Intel® Quartus® Prime compilation and timing closure aids, refer to the External Memory Interfaces IP - Support Center website.

Essential Documentation

Documentation Description
Intel® Agilex™ General Purpose I/O and LVDS SERDES User Guide

The Intel® Agilex™ General Purpose I/O and LVDS SERDES User Guide describes the I/O column architecture and where the specific Hard Memory Controller block accessible to the HPS resides,

For guidance on connecting the HPS-accessible hard memory controller block to the HPS, refer to Package Selection and I/O Vertical Migration Support of the Intel® Agilex™ General Purpose I/O and LVDS SERDES User Guide. This section shows the I/O row and bank locations for all device and package combinations across all Intel® Agilex™ family variants, including the relative location of the HPS to its accessible banks.

Intel® Agilex™ FPGA External Memory Interface Overview

The Intel® Agilex™ External Memory Interfaces User Guide includes the details required to understand what specific I/O banks are used for HPS external memory interfaces and where address/command, ECC and data signals are located. The user guide also consists of important information on restrictions on the placement of these external memory interface signals within the banks and any flexibility the designer has in varying from the default placement. While Intel recommends that you familiarize yourself with all the content available in this user guide, understanding the following sections is a prerequisite to properly design the Intel® Agilex™ EMIF for the HPS IP in your application.

  • Intel® Agilex™ EMIF IP Product Architecture chapter—This section describes in greater detail the I/O Row, HMC, I/O lanes, and the hardened feature support for DDR SDRAM memories in the I/O elements.
  • Restrictions on I/O Bank Usage for Intel® Agilex™ EMIF IP with HPS chapter—This section provides a diagram that shows the specific I/O bank and lane locations for address/command, ECC, and data signals.

The following design guidelines supplement the information found in the above referenced documentation.