AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

6.1.7.2. PLL Board Design Guidelines

Table 57.  PLL Board Design Guidelines Checklist
Number Done? Checklist Item
1   Connect all PLL power pins to reduce noise even if the design does not use all the PLLs.
2   Power supply nets should be provided by an isolated power plane, a power plane cut out, or thick trace of at least 20 mils.

Plan your board design when you design a power system for PLL usage and to minimize jitter, because PLLs contain analog components embedded in a digital device.

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