1. Introduction to the Intel® Agilex™ Device Design Guidelines 2. System Specification 3. Device Selection 4. Security Considerations 5. Design Entry 6. Board and Software Considerations 7. Design Implementation, Analysis, Optimization, and Verification 8. Debugging 9. Embedded Software Design Guidelines for Intel® Agilex™ SoC FPGAs
5.1.1. Firewall Planning 5.1.2. Boot And Configuration Considerations 5.1.3. HPS Clocking and Reset Design Considerations 5.1.4. Reset Configuration 5.1.5. HPS Pin Multiplexing Design Considerations 5.1.6. HPS I/O Settings: Constraints and Drive Strengths 5.1.7. Design Guidelines for HPS Interfaces 5.1.8. Interfacing between the FPGA and HPS 5.1.9. Implementing the Intel® Agilex™ HPS Component
7.1. Selecting a Synthesis Tool 7.2. Device Resource Utilization Reports 7.3. Intel® Quartus® Prime Messages 7.4. Timing Constraints and Analysis 7.5. Area and Timing Optimization 7.6. Preserving Performance and Reducing Compilation Time 7.7. Designing with Intel® Hyperflex™ 7.8. Simulation 7.9. Power Analysis 7.10. Power Optimization 7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
9.1. Overview 9.2. Golden Hardware Reference Design (GHRD) 9.3. Define Software Requirements 9.4. Define Software Architecture 9.5. Selecting Software Tools 9.6. Choosing the Bootloader Software 9.7. Selecting an Operating System for Your Application 9.8. Assembling Your Software Development Platform for Linux* 9.9. Assembling your Software Development Platform for Partner OS or RTOS 9.10. Driver Considerations 9.11. Boot And Configuration Considerations 9.12. System Reset Considerations 9.13. Flash Considerations 9.14. Develop Application 9.15. Test and Validate 9.16. Embedded Software Design Guidelines Revision History
2.7. Using Intel® Agilex™ HPS in your Device
Take note of HPS components you must consider when planning your system design.
|1||HPS_OSC_CLK (mandatory)— there are other ways to clock the HPS, but this is the most common and easiest way.|
|2||HPS_COLD_nRESET (optional)—if you want external reset control over the HPS, this is the easiest way to achieve it.|
|3||HPS_EMIF (mandatory)—the HPS is designed to run software out of a large DDR style memory. Not provisioning the HPS_EMIF makes the software environment constrained and in most cases unusable.|
|4||HPS_UART (mandatory)—pin one of these out on the HPS dedicated pins so you can see early boot telemetry from your software.|
|5||HPS_JTAG (mandatory)—this is mandatory for board bring up and debugging early boot flow issues. This can be serially chained with the SDM JTAG TAP or broken out on HPS dedicated pins.|
|6||HPS_EMAC (optional)—if you can allocate one of these you can provide luxury debug and maintenance support for the software environment.|
|7||HPS flash memory (optional)—since the HPS is loaded by the SDM and the HPS can subsequently access the SDM flash, this may not be mandatory. Many software environments require some sort of persistent storage.|
Did you find the information on this page useful?