AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

2.7. Using Intel® Agilex™ HPS in your Device

Take note of HPS components you must consider when planning your system design.

Table 11.  Considerations for using Intel® Agilex™ SoC in your Device Checklist
Number Done? Checklist Item
1   HPS_OSC_CLK (mandatory)— there are other ways to clock the HPS, but this is the most common and easiest way.
2   HPS_COLD_nRESET (optional)—if you want external reset control over the HPS, this is the easiest way to achieve it.
3   HPS_EMIF (mandatory)—the HPS is designed to run software out of a large DDR style memory. Not provisioning the HPS_EMIF makes the software environment constrained and in most cases unusable.
4   HPS_UART (mandatory)—pin one of these out on the HPS dedicated pins so you can see early boot telemetry from your software.
5   HPS_JTAG (mandatory)—this is mandatory for board bring up and debugging early boot flow issues. This can be serially chained with the SDM JTAG TAP or broken out on HPS dedicated pins.
6   HPS_EMAC (optional)—if you can allocate one of these you can provide luxury debug and maintenance support for the software environment.
7   HPS flash memory (optional)—since the HPS is loaded by the SDM and the HPS can subsequently access the SDM flash, this may not be mandatory. Many software environments require some sort of persistent storage.

Did you find the information on this page useful?

Characters remaining:

Feedback Message