AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

3.2. PLLs and Clock Routing

Table 14.  PLLs and Clock Routing Checklist
Number Done? Checklist Item
1   Verify the number of PLLs and clock resources.

Verify that your chosen device density package combination includes enough PLLs and clock routing resources for your design.

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