AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

9.13.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage

The QSPI device connected to the SDM can also be accessed directly by the HPS. However, there is a significant speed penalty when doing so. It is up to you to decide whether the speed penalty is acceptable for the end application.

For reference, here are some performance numbers:

  • Maximum HPS eMMC read speed: 50Mbytes/s
  • Maximum HPS SD read speed: 25Mbytes/s
  • Maximum HPS read speed from SDM QSPI: 4Mbytes/s

GUIDELINE: For best performance, Intel® recommends to use a flash device connected to HPS for mass storage by HPS.

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