AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022
Public
Document Table of Contents

6.3.1.1. Unused Pins

Table 79.  Unused Pins Checklist
Number Done? Checklist Item
1   Specify the reserved state for unused I/O pins.
2   Carefully check the pin connections in the Intel® Quartus® Prime software-generated .pin file. Do not connect RESERVED pins.

You can specify the state of unused pins in the Intel® Quartus® Prime software to allow flexibility in the board design by choosing one of the five allowable states for Reserve all unused pins on the Unused Pins category in the Device and Pin Options dialog box:

  • As inputs tri-stated
  • As output driving ground
  • As outputs driving an unspecified signal
  • As input tri-stated with bus-hold circuitry
  • As input tri-stated with weak pull-up

The common setting is to set unused pins As inputs tri-stated with weak pull-up. To improve signal integrity, set the unused pins to As output driving ground. Doing this reduces inductance by creating a shorter return path and reduces noise on the neighboring I/Os. This approach should not be used if this results in many via paths causing congestion for signals under the device.

To reduce power dissipation, set clock pins and other unused I/O pins As inputs tri-stated and tie them to ground.

Connection Guidelines for Unused HPS Block

If you are not using the HPS block in the Intel® Agilex™ SoC device, you can follow the guidelines below for HPS specific pins:

Table 80.  HPS Supply Pins
Pin Function If HPS is unused, connect to:

VCCL_HPS

VCCIO_HPS

VCCPLL_HPS

VCCPLLDIG_HPS

If you do not intend to utilize the HPS in the Intel® Agilex™ SoC device, you must still provide power to the HPS power supplies. Do not leave the HPS power supplies floating or connect them to GND.

For more information, refer to HPS Supply Pins section in the Intel® Agilex™ Device Family Pin Connection Guidelines .

48 HPS Dedicated IO No connect (NC)

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