CLK_[T,B]_2[A,B,C,D]_[0:1][p,n]

CLK_[T,B]_3[A,B,C,D]_[0:1][p,n]

Dedicated high speed clock input pins that can be used for data inputs or outputs. Differential input OCT Rd, single-ended input OCT Rt, and single-ended output OCT Rs are supported on these pins.

When you do not use these pins as dedicated clock pins, you can use them as regular I/O pins.

Supported I/O standards:

• 1.2 V
• True Differential Signaling

Maximum clock frequency is 400 MHz.

Edge rate is 250 ps at 20–80%.

These pins have an internal 10-kΩ pull up.

PLL_[2][A,B,C,D]_[T,B]_FB[0:1]

PLL_[3][A,B,C,D]_[T,B]_FB[0:1]

Dual-purpose I/O pins that can be used as single-ended inputs, single-ended outputs, or external feedback input pins.

For more information about the supported pins, refer to the device pin-out file.

Supported I/O standards:

• 1.2 V
• True Differential Signaling

Maximum clock frequency is 400 MHz.

Edge rate is 250 ps at 20–80%.

These pins have an internal 10-kΩ pull up.

PLL_[2][A,B,C,D]_[T,B]_CLKOUT[0:1][p,n]

PLL_[3][A,B,C,D]_[T,B]_CLKOUT[0:1][p,n]

I/O pins that can be used as two single-ended clock output pins or one differential clock output pair.

For more information about the supported pins, refer to the device pin-out file.

Supported I/O standards:

• 1.2 V
• True Differential Signaling

Maximum clock frequency is 400 MHz.

Edge rate is 250 ps at 20–80%.

These pins have an internal 10-kΩ pull up.

Dedicated JTAG test clock input pin located in the Secure Device Manager (SDM) bank.

This pin can also be used to access the HPS JTAG chain. For more information, refer to the HPS JTAG Pins.

This pin support the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-down resistor.

JTAG clock speed is 33 MHz for JTAG split mode. In the JTAG split mode, the SDM JTAG mode is independent of the HPS JTAG.

JTAG clock speed is 22 MHz for JTAG daisy-chain mode. In the JTAG daisy-chain mode, the HPS DAP TAP is daisy chained with the SDM mTAP.

Connect this pin through a 1-kΩ pull-down resistor to GND.

Dedicated JTAG test mode select input pin located in the SDM bank.

This pin can also be used to access the HPS JTAG chain. For more information, refer to the HPS JTAG Pins.

This pin support the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-up resistor.

Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TMS pin to the VCCIO_SDM supply using a 1-kΩ resistor.

Dedicated JTAG test data output pin located in the SDM bank.

This pin can also be used to access the HPS JTAG chain. For more information, refer to the HPS JTAG Pins.

This pin support the 1.8-V single-ended I/O standard.

Dedicated JTAG test data input pin located in the SDM bank.

This pin can also be used to access the HPS JTAG chain. For more information, refer to the HPS JTAG Pins.

This pin support the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-up resistor.

Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TDI pin to the VCCIO_SDM supply using a 1-kΩ resistor.

Configuration status pin. This pin is used for synchronization with the configuration host driving nCONFIG and to report errors.

This pin support the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-up resistor.

The drive strength is 8 mA.

When you are using the Avalon^® streaming configuration scheme, connect this pin to the configuration host.

For other configuration schemes, you can use this pin to monitor the configuration status.

This pin must be pulled up through a 10-kΩ resistor to VCCIO_SDM for all configuration schemes.

The nCONFIG pin is used to clear the device and prepare for reconfiguration.

This pin support the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-up resistor.

When you use the Avalon^® streaming configuration scheme, connect this pin to the configuration host.

When you use other configuration schemes, pull this pin to VCCIO_SDM through an external 10-KΩ pull-up resistor. This pin can be used to restart configuration by driving it low and then high again. Ensure that you follow all the requirements for the nCONFIG operation as specified in the Intel^® Agilex™ Configuration User Guide and AN 886: Intel^® Agilex™ SoC Device Design Guidelines.

Reference clock source for SDM PLL.

This pin is used as the clock for device configuration and transceiver calibration.

This pin support the 1.8-V single-ended I/O standard.

This pin has an internal 20-kΩ pull-down resistor.

You must provide an external clock source to this pin if you are using transceivers.

If you choose to use the external clock source for configuration and/or instantiate any transceivers in your design, you must provide a 25-MHz, 100-MHz, or 125-MHz free-running clock source to this pin and enable it in the Intel^® Quartus^® Prime software when you compile your design.

If you are using the internal oscillator for configuration and do not instantiate any transceivers in your design, leave this pin unconnected.

Dual-purpose configuration data input pins.

Use AVST_DATA[15:0] pins for Avalon^® Streaming Interface ( Avalon^® -ST) x16 mode, AVST_DATA [31:0] pins for Avalon^® -ST x32 mode, or as regular I/O pins.

This pin support the 1.2-V LVCMOS I/O standard.

This pin has a 10-kΩ internal pull-up resistor.

Dual-purpose Avalon^® -ST interface data ready output pin. This pin is used for the Avalon^® -ST x16 and x32 configuration schemes.

This pin cannot be used as a user I/O pin if you are using the AvST x16 or AvST x32 configuration scheme.

This pin supports the 1.2-V LVCMOS I/O standard.

This pin has a 10-kΩ internal pull-up resistor.

Dual-purpose Avalon^® -ST interface clock input pin. This pin is used for the Avalon^® -ST x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

This pin supports the 1.2-V LVCMOS I/O standard.

This pin has a 10-kΩ internal pull-up resistor.

Connect this pin to the clock signal of the external configuration controller when configuring using the Avalon^® -ST x16 or x32 interface.

Connect unused pins as defined in the Intel^® Quartus^® Prime software.

Dual-purpose configuration data valid pin. This pin is used for the Avalon^® -ST x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

This pin supports the 1.2-V LVCMOS I/O standard.

This pin has a 10-kΩ internal pull-up resistor.

Connect this pin to the data valid signal of the external configuration controller when configuring using the Avalon^® -ST x16 or x32 interface.

Connect unused pins as defined in the Intel^® Quartus^® Prime software.

DIFF_RX[2][A,B,C,D][1:24][p,n]

DIFF_RX[3][A,B,C,D][1:24][p,n]

These are SERDES receiver channels on GPIO banks. If these pins are not used in SERDES implementation, these pins are available as user I/O pins.

Supported I/O standards:

• 1.5-V I/O standard for true differential I/O
• 1.2-V I/O standard for single-ended voltage referenced and non-voltage referenced I/O
• 1.2-V I/O standard for differential voltage referenced I/O

These pins have an internal 10-kΩ pull-up resistor.

DIFF_TX[2][A,B,C,D][1:24][p,n]

DIFF_TX[3][A,B,C,D][1:24][p,n]

These are SERDES transmitter channels on GPIO banks. If these pins are not used in SERDES implementation, these pins are available as user I/O pins.

Supported I/O standards:

• 1.5-V I/O standard for true differential I/O
• 1.2-V I/O standard for single-ended voltage referenced and non-voltage referenced I/O
• 1.2-V I/O standard for differential voltage referenced I/O

These pins have an internal 10-kΩ pull-up resistor.

Optional data strobe signal for use in external memory interfacing. These pins drive to the dedicated DQS phase shift circuitry.

Supported I/O standards:

• POD 1.2-V I/O standard
• SSTL 1.2-V I/O standard

Optional complementary data strobe signal for use in external memory interfacing. These pins drive to the dedicated DQS phase shift circuitry.

Supported I/O standards:

• POD 1.2-V I/O standard
• SSTL 1.2-V I/O standard

Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, if you plan on migrating to a different memory interface that has a different DQ bus width, you need to reevaluate your pin assignments. Analyze the available DQ pins across all pertinent DQS columns in the device pin-out file.

Supported I/O standards:

• POD 1.2-V I/O standard
• SSTL 1.2-V I/O standard

Tie these pins to GND.

Tie these pins to GND if you do not use the voltage sensor feature. For more information on the usage of these pins, refer to the Intel^® Agilex™ Power Management User Guide. Do not drive the VSIGP and VSIGN pins until the VCCADC power rail has reached 1.62 V to prevent damage.

Connect these pins to an external temperature sensing device to allow sensing of the FPGA's temperature. If you do not use the temperature sensing diode with an external temperature sensing device, leave these pins unconnected.

For more information about the locations and channel numbers of the temperature sensors, refer to the Intel^® Agilex™ Sensor Monitoring System chapter in the Intel^® Agilex™ Power Management User Guide.

Connect these pins to an external temperature sensing device to allow sensing of the E-tile or P-tile temperature. If you do not use the temperature sensing diode with an external temperature sensing device, leave these pins unconnected.

For more information about the locations and channel numbers of the temperature sensors, refer to the Intel^® Agilex™ Sensor Monitoring System chapter in the Intel^® Agilex™ Power Management User Guide.

These pins connect to the internal temperature sensing diode in the R-tile.

Connect these pins to an external temperature sensing device to allow sensing of the R-tile temperature. If you do not use the temperature sensing diode with an external temperature sensing device, leave these pins unconnected.

For more information about the locations and channel numbers of the temperature sensors, refer to the Intel^® Agilex™ Sensor Monitoring System chapter in the Intel^® Agilex™ Power Management User Guide.

RZQ_[T,B]_2[A,B,C,D]

RZQ_[T,B]_3[A,B,C,D]

Reference pins for I/O banks. The RZQ pins share the same VCCIO_PIO with the I/O bank where they are located.

Connect the external precision resistor to the designated pin within the bank. If not required, this pin is a regular I/O pin.

These pins support 1.2-V I/O standard.

These pins have an internal 10-kΩ pull-up resistor.

When using OCT, tie these pins to GND through a 240-Ω resistor.

When you do not use these pins as dedicated input for the external precision resistor or as I/O pins, leave these pins unconnected.

Do not connect to power, GND, or any other signal. These pins must be left floating.

When designing for device migration, you have the option to connect these pins to either power, GND, or a signal trace depending on the pin assignment of the devices selected for migration.

However, if device migration is not a concern, leave these pins floating.

VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator.

For details about the recommended operating conditions, refer to the Electrical Characteristics section in the Intel^® Agilex™ Device Data Sheet.

Use the Intel^® FPGA Power and Thermal Calculator and the Intel^® Quartus^® Prime Power Analyzer to determine the current requirements for VCCP and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board.

VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator.

For details about the recommended operating conditions, refer to the Electrical Characteristics section in the Intel^® Agilex™ Device Data Sheet.

Use the Intel^® FPGA Power and Thermal Calculator and the Intel^® Quartus^® Prime Power Analyzer to determine the current requirements for VCC and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board.

Connect VCCPT to a 1.8-V low noise switching regulator. You have the option to source the following from the same regulator as VCCPT:

• VCCPLL_SDM, VCCPLL_HPS, and VCCADC with proper isolation filtering

Voltage spike ringing may be observed on VCCPT during device power-down sequencing if VCC is powered down before VCCPT, with the magnitude of the voltage spike ringing higher than VCCPT. This is the expected behavior and will neither cause any functional failure nor reliability concerns to the device.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel^® Agilex™ Devices.

Connect the VCCR_CORE to 1.2-V power supply.

You have the option to source VCCR_CORE from the same regulator as VCCIO_PIO only when you are using the DDR4 I/O standard with proper isolation filtering.

Connect all VCCH pins to a 0.9-V low noise switching power supply for Intel^® Agilex™ devices with E-tile and P-tile.

Connect all VCCH pins to a 0.8-V low noise switching power supply for Intel^® Agilex™ devices with F-tile and R-tile.

For more details, refer to the Intel^® Agilex™ Device Data Sheet.

Connect this pin to the VCCH voltage rail in the Intel^® Agilex™ devices with E-tile and P-tile.

Connect this pin to the VCC_HSSI_GXR voltage rail in the Intel^® Agilex™ devices with F-tile and R-tile.

For Intel^® Agilex™ production devices and other Intel^® Agilex™ ES (except 2486A package) devices, connect VCCA_PLL to a 1.2-V low noise switching regulator. You have the option to source VCCA_PLL from the same regulator as VCCIO_PIO with proper isolation filtering. The VCCA_PLL rail must reside in Group 3 power rails.

VCCIO_PIO[2][A,B,C,D]

VCCIO_PIO[3][A,B,C,D]

These are the supply voltage pins for the I/O banks. Each bank can support a different voltage level.

Supported VCCIO standards include the following:

• 1.2-V LVCMOS
• SSTL12/Diff SSTL12
• HSTL12/ Diff HSTL12
• HSUL12/ Diff HSUL12
• POD12/ Diff POD12
• True Differential Signaling

Connect these pins to a 1.2-V or 1.5-V power supplies, depending on the I/O standard required by the specific bank.

Connect the unused I/O bank power to 1.2V or 1.5V if the I/O bank will be used in future. Connect unused I/O bank power to GND and I/O pins floating if the I/O bank will not be used in future. Do not leave the I/O power floating.

During the power-up sequence only, a transient current whose magnitude is less than the VCCIO_PIO operating static current may be observed as the VCCIO_PIO transistors become operational. This is the expected behavior and will neither cause any functional failure nor reliability concerns to the device if the power-up or power-down sequence is followed.

For more details, refer to the Intel^® Agilex™ Sensor Monitoring System chapter in the Intel^® Agilex™ Power Management User Guide.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel^® Agilex™ Devices.

Connect these pins to a 1.8-V power supply.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel^® Agilex™ Devices.

When using the device security AES BBRAM key, connect this pin to a non-volatile battery power source in the range of 1.0 V – 1.8 V.

When not using the AES BBRAM key, tie this pin to the 1.8-V VCCPT.

Provide a minimum decoupling of 47nF for the VCCBAT power rail near the VCCBAT pin.

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Intel^® Agilex™ Devices.

With proper isolation filtering, you have the option to source VCCPLL_SDM from the same regulator as VCCPT.

Decoupling for these pins depends on the design decoupling requirements of the specific board.

VREFB[2][AN0,BN0,CN0,DN0]

VREFB[3][AN0,BN0,CN0,DN0]

If VREF pins are not used, connect them to GND.

VCCLSENSE and GNDSENSE are differential remote sense pins for the VCC power. Connect your regulators’ differential remote sense lines to the respective VCCLSENSE and GNDSENSE pins. This compensates for the DC IR drop associated with the PCB and device package from the VCC power. Route these connections as differential pair traces and keep them isolated from any other noise source.

You must connect the VCCLSENSE and GNDSENSE lines to the regulator’s remote sense inputs.

You must supply a low noise 1.8-V power supply to this pin if you are using the internal voltage sensors of the Intel^® Agilex™ device.

When you are using the voltage sensors, tie this pin to VCCPT with proper isolation filtering.

Reference resistor input for the PLLs of the SDM interface.

Connect a 2-kΩ +/-1% resistor to GND.

This pin is pulled low internally by a 20-kΩ resistor when the device is powered up.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin will function as MSEL[0] during power up and reset to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Intel^® Agilex™ Configuration User Guide.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin will function as MSEL[1] during power up to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Intel^® Agilex™ Configuration User Guide.

This pin is pulled low internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

Connect this pin to the nCS input of the fourth QSPI flash device when you use cascaded QSPI flash devices for HPS application.

Connect with a 1-kΩ pull-up resistor to VCCIO_SDM.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin will function as MSEL[2] during power up to determine the configuration scheme. Once the pin completes the MSEL function, it will then function according to the configuration scheme you have selected.

For more information, refer to the Intel^® Agilex™ Configuration User Guide.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

This pin is pulled high internally by a 20-kΩ resistor when the device is powered up.

This pin functions differently depending on the configuration scheme used by setting the MSEL pins.

PMBus Power Management Clock.

This pin is used as the clock pin for the PMBus interface.

This pin requires a pull-up resistor to the 1.8-V VCCIO_SDM supply. Intel^® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8 V.

Connect this pin to the PMBus clock pin of your regulator.

When a –V or –E power option device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. You can do this by connecting the PWRMGT_SCL and PWRMGT_SDA signals to the VCC voltage regulator for the PMBus master mode and the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals to the external master controller for the PMBus slave mode.

SDM_IO0

SDM_IO14

SDM_IO0

SDM_IO0

SDM_IO14

SDM_IO0

SDM_IO14

PMBus Power Management Serial Data.

This pin is used as the data pin for the PMBus interface.

This pin requires a pull-up resistor to the 1.8-V VCCIO_SDM supply. Intel^® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8V.

Connect this pin to the PMBus data pin of your regulator.

When a –V or –E power option device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. You can do this by connecting the PWRMGT_SCL and PWRMGT_SDA signals to the VCC voltage regulator for the PMBus master mode and the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals to the external master controller for the PMBus slave mode.

SDM_IO11

SDM_IO12

SDM_IO16

SDM_IO12

SDM_IO16

SDM_IO11

SDM_IO12

SDM_IO16

SDM_IO11

SDM_IO12

SDM_IO16

PMBus Power Management Alert.

This pin is used as the ALERT function for the PMBus interface when the Intel^® Agilex™ –V or –E power option device is the PMBus slave.

This pin requires a pull-up resistor to the 1.8-V VCCIO_SDM supply. Intel^® recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8 V.

Connect this pin to the PMBus ALERT pin of the external master controller.

When using the SmartVID feature with the Intel^® Agilex™ –V or –E power option device as a PMBus slave, you must connect the PWRMGT_ALERT signal along with the PWRMGT_SCL and PWRMGT_SDA signals to the PMBus master device to complete the SmartVID power management interface. The PMBus master device reads the VID codes from the Intel^® Agilex™ slave and programs the voltage regulator to output the correct VID voltage.

SDM_IO0

SDM_IO12

SDM_IO0

SDM_IO9

SDM_IO12

SDM_IO0

SDM_IO9

SDM_IO12

SDM_IO0

SDM_IO12

The CONF_DONE pin indicates all configuration data has been received.

By default, Intel^® recommends using the SDM_IO16 pin to implement the CONF_DONE function.

If SDM_IO16 is unavailable, the CONF_DONE function can also be implemented using any unused SDM_IO pins.

Except for SDM_IO0 and SDM_IO16, other SDM_IO pins are required to connect to an external 4.7-kΩ pull-down resistor for the CONF_DONE signal.

Connect the CONF_DONE pin to the external configuration controller when configuring using the Avalon^® -ST (AVST) interface.

You have an option to monitor this signal with an external component if you are using the active serial (AS) x4 configuration scheme.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO6

SDM_IO7

SDM_IO8

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO8

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

The INIT_DONE pin indicates the device has enter user mode upon completion of configuration. When used for this purpose, this pin must be enabled by the Intel^® Quartus^® Prime software.

When the INIT_DONE function is enabled, this pin will drive high when configuration is completed and the device goes into user mode.

Intel^® recommends you to use SDM_IO0 or SDM_IO16 to implement the INIT_DONE function when available as it has an internal weak pull-down for the correct function of INIT_DONE during power up.

If SDM_IO0 and SDM_IO16 are unavailable, SDM_IO5 can also be used for the INIT_DONE function when the configuration mode is set to Avalon^® –ST x8 or Avalon^® –ST x32 (AVST x8 or AVST x32) as these modes require an external 4.7–kΩ pull-down resistor.

If SDM_IO0, SDM_IO5, and SDM_IO16 are unavailable, the INIT_DONE function can also be implemented using any unused SDM_IO pins provided that an external 4.7–kΩ pull-down resistor is provided for the INIT_DONE signal.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO6

SDM_IO7

SDM_IO8

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO8

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

The CvP_CONFDONE pin indicates the device has received the complete bitstream during configuration via protocol (CvP) core image configuration.

When used for this purpose, enable this pin using the Intel^® Quartus^® Prime software.

Connect this output pin to an external logic device that monitors the CvP operation. The VCCIO_SDM power supply must meet the input voltage specification of the receiving side.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO7

SDM_IO9

SDM_IO12

SDM_IO16

The SEU_ERROR pin drives high to indicate there is an SEU error message inside the SEU error queue. This pin stays high whenever the error message queue contains one or more error messages.

The SEU_ERROR signal goes low only when the SEU error message queue is empty. When used for this purpose, enable this pin using the Intel^® Quartus^® Prime software.

Connect this output pin to an external logic device that monitors the SEU event.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO7

SDM_IO9

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

This is an active low, bidirectional pin. By default, this pin acts as an input pin to the SDM. When asserted externally for at least 5ms, this pin will generate interrupt to the SDM. The SDM will then initiate a cold reset procedure to the HPS and its peripherals. If the cold reset is generated from internal sources (for example, the HPS EL3 software), the SDM will switch this pin to output and drive a pulse to indicate reset. Once the cold reset procedure is complete, this pin will be switched back to input.

Connect this pin through a 1–10-kΩ pull up to the VCCIO_SDM supply. Do not connect this pin to the reset input of any connected quad serial peripheral interface (quad SPI) devices.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO7

SDM_IO9

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

Direct to factory input pin.

When using the remote system upgrade feature, this optional pin allows you to choose between factory or application image. Driving logic high into this pin will instruct the device to load factory image, while driving logic low into this pin will instruct the device to load the application image.

Connect this input pin to an external logic device that manages the remote system upgrade of the device. By default, the external logic should provide logic low to this pin so that the application image will be the default image of the device, and only switch to factory image if required.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16

SDM_IO0

SDM_IO5

SDM_IO7

SDM_IO9

SDM_IO12

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO1

SDM_IO2

SDM_IO3

SDM_IO4

SDM_IO5

SDM_IO6

SDM_IO7

SDM_IO9

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO15

SDM_IO16

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16

Connect VCCH_GXE to a 1.1-V low noise switching regulator.

VCCH_GXE must be powered up even when the E-tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

VCCRT_GXE can be connected to a 0.9-V low noise switching regulator.

You must connect VCCRT_GXE to VCCH through an LC filter. For more information about the LC filter design, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

VCCRT_GXE must be powered up even when the E-tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

You must source the VCCRTPLL_GXE from the VCCH with proper isolation filtering.

Filtering may be optional if this voltage rail can meet the noise mask requirement. For more information about the noise mask requirements, refer to the Intel^® Agilex™ Power Management User Guide.

VCCRTPLL_GXE must be powered up even when the E-tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

Connect VCCCLK_GXE to a 2.5-V low noise switching regulator.

VCCCLK_GXE must be powered up even when the E-tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

Connect VCC_HSSI_GXE to a 0.9-V low noise switching regulator. This voltage rail must be shared with VCCH.

VCC_HSSI_GXE must be powered up even when the E-tile transceivers are not used.

GXE(L8,R9)_RX_CH[0:23][p,n]

High speed differential serial inputs to receiver circuitry. Specific to the E-tile transceiver on the left (L) side or right (R) side of the device.

Supported I/O standard:

• 57.8G PAM4
• 28.9G NRZ

No off-chip AC-coupling capacitor is required if the RX input common mode is between VCCRT_GXE and GND, and the RX input amplitude difference is less than 1200 mVp-p. The absolute maximum input to the E-Tile SerDes is VCCRT_GXE + 300 mV to prevent forward biasing of the ESD diodes.

When using external AC-coupling capacitors, the RX termination is to the VCCH_GXE supply. For more information about the external AC-coupling, refer to the E-Tile Transceiver PHY User Guide.

Leave unused pins floating.

High speed differential serial outputs from the transmitter circuitry. Specific to the E-tile transceiver on the left (L) side or right (R) side of the device.

Supported I/O standard:

• 57.8G PAM4
• 28.9G NRZ

High speed differential reference clock connects to the E-tile transceiver of the left (L) side or right (R) side of the device.

REFCLK_GXE is supplied to both RX and TX independently.

REFCLK_GXE can be used as dedicated clock input pins for core clock generation by configuring transceiver channel (Native PHY IP core) in the PLL mode.

Supported I/O standard:

• LVPECL

No off-chip termination capacitor is required. The default internal REFCLK inputs are 2.5-V LVPECL with a 50-Ω termination.

Optional external termination is 2.5-V LVPECL or 3.3-V LVPECL. For more information about the external termination, refer to the Reference Clock Pins section of the E-Tile Transceiver PHY User Guide.

Tie each unused REFCLK pin to GND through a 1-kΩ resistor.

REFCLK[1] must always be bonded out on board and connected to a clock source in case dynamic reconfiguration of REFCLK is planned. For more details on how to use it, refer to the Dynamic Reconfiguration Flow for Special Cases section of the E-Tile Transceiver PHY User Guide.

Preservation of unused transceiver channels may need extra REFCLK_GXE to be bonded out on board based on use cases. For more details, refer to the Unused Transceiver Channels section of the E-Tile Transceiver PHY User Guide.

The input reference clock must be stable and free-running at FPGA power-up for proper PLL calibrations and a successful configuration.

Precision reference resistor for the AIB auxiliary channel.

Not all pins are available in each device density and package combination. For more information, refer to the specific device pin-out file.

Secondary high-voltage analog supply for transceivers, and on-die PLL specific to P-tile.

Connect VCCH_GXP to a 1.8-V low noise switching regulator. This voltage rail can be shared with VCCPT using proper isolation filtering.

To minimize regulator switching noise impact on channel jitter performance, keep the regulator switching frequency below 1MHz.

VCCH_GXP must be powered up even when the P-tile transceivers are not used. For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

Primary analog supply for the TX and RX channels, specific to P-tile.

Connect VCCRT_GXP to a 0.9-V low noise switching regulator. This voltage rail can be shared with VCCH using proper isolation filtering.

VCCRT_GXP must be powered up even when the P-tile transceivers are not used. For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

LVCMOS I/O buffer supply rail, specific to P-tile.

Connect VCCCLK_GXP to a 1.8V low noise switching regulator. This voltage rail can be shared with VCCPT using proper isolation filtering.

VCCCLK_GXP must be powered up even when the P-tile transceivers are not used. For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

Required power supply for the firmware to read internal settings for the one-time programmable eFuses.

Connect this voltage rail to a 0.9-V power supply. This rail must be shared with VCC_HSSI_GXP.

VCCFUSE_GXP must be powered up even when the P-tile transceivers are not used. For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Intel^® Agilex™ Power Distribution Network Design Guidelines.

Primary digital supply for all digital signals, specific to P-tile.

Connect VCC_HSSI_GXP to a 0.9-V low noise switching regulator. This voltage rail must be shared with VCCH.

VCC_HSSI_GXP must be powered up even when the P-tile transceivers are not used.

PCIe* Gen4-based receiver pins, specific to the P-tile transceivers on the left (L) side of the device.

When these pins are not used, they must be tied via a 1kΩ pull-down resistor to GND.

PCIe* Gen4-based transmitter pins, specific to the P-tile transceivers on the left (L) side of the device.

Transmitter pins must be AC coupled. The capacitor value ranges from 176 nF to 256 nF per PCIe* Gen4 specification.

When these pins are not used, they must be floating.

For HCSL I/O standard, it only supports DC coupling.

You must connect a 100-MHz reference clock to both reference clock inputs for x16 and 4x4 modes. These reference clocks must be derived from the same clock source. A fan-out buffer can be used but must meet a ± 300 ppm requirement.

For 2x8 modes, you can connect both reference clock inputs to the same clock source or connect to two independent clock sources.

If the P-tile is completely unused, tie both REFCLK inputs to GND.

Unused reference clock pins must be tied to 1kΩ pull-down resistor to GND.

Reference resistor for the Embedded Multi-Die-Interconnect Bridge (EMIB) of the P-tile transceivers.

Not all pins are available in each device density and package combination. For more information, refer to the specific device pin-out file.

Connect each IO_AUX_RREF to a 2.8 kΩ resistor (±1%) to GND.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.

Transceiver reference resistor connection for PMA circuitry to provide termination for calibration.

Not all pins are available in each device density and package combination. For more information, refer to the specific device pin-out file.

Connect each pin to a 169Ω 1% (100 ppm/°C) precision resistor to GND.

Place this resistor very close to the IO_RESREF pin. Avoid routing any noisy signals next to this reference resistor or its traces. Tie resistor to GND plane through a via placed very close to the reference resistor.

External reference resistor parasitic capacitance load must be less than 14 pF. Maximum parasitic capacitance includes external loading of PHY count, package trace, and PCB trace. Each PHY connected to the IO_RESREF pin adds an additional 1.5 pF of loading.

In a PCI Express* ( PCIe* ) adapter card implementation, connect the PCIe* nPERST signal from the PCIe* edge connector to each P-tile transceiver bank I_PIN_PERST_N input.

Use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe* connector to the 1.8-V I_PIN_PERST_N input of each P-tile transceiver that is used on the board.

Provide a 1.8-V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3-V PCIe* nPERST signal on the adapter card.

If the tile is unused, tie to GND.

In cases where two independent clock sources are used for 2x8 bifurcation mode, ensure I_PIN_PERST_N be de-asserted high after both reference clocks are stable.

Connect VCC_HSSI_GXF to low noise switching regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCCH_FGT_GXF should share 1.8-V rail with VCCPT through ferrite bead. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for fitter details and decoupling capacitor requirement.

Tie to GND if this tile is not used.

Connect VCCEHT_FHT_GXF to dedicated regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if there is no FHT channel used.

Connect VCCERT_FGT_GXF to dedicated regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

This analog supply should not share with others.

Tie to GND if this tile is not used.

Connect VCCERT1_FHT_GXF to dedicated regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

This analog supply should not share with others.

Tie to GND if there is no FHT channel used.

Connect VCCERT2_FHT_GXF to dedicated regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

This analog supply should not share with others.

Tie to GND if there is no FHT channel used.

VCCFUSECORE_GXF should share 1.0-V rail from power group 2. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCCFUSEWR_GXF should share 1.0-V rail from power group 2. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Tie to GND if this tile is not used

VCCCLK_GXF should share 1.8-V rail with VCCPT through ferrite bead. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for filter details and decoupling capacitor requirement.

Tie to GND if this tile is not used.

VCC_SENSE_FHT_GXF and VSS_SENSE_FHT_GXF are differential remote sense pins for the VCCERT1_FHT_GXF power. Connect the differential remote sense lines of the regulator to the respective VCC_SENSE_FHT_GXF and VSS_SENSE_FHT_GXF pins. This compensates for the DC IR drop associated with the PCB and device package from the VCCERT1_FHT_GXF power. Route these connections as differential pair traces and keep them isolated from any other noise source.

You must connect the VCC_SENSE_FHT_GXF and VSS_SENSE_FHT_GXF lines to the remote sense inputs of the regulator.

Tie to GND if there is no FHT channel used.

Connect each GXF_RCOMP_P_FHT pin with a 1.5-KΩ resistor (0.1%) to the GXF_RCOMP_N_FHT pin.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.

If this tile is unused, you must connect the 1.5-KΩ resistor between the GXF_RCOMP_P_FHT and GXF_RCOMP_N_FHT pin.

Connect each GXF_RCOMP_P_Q2_CH1_FGT pin with a 499-Ω resistor (0.1%) to the GXF_RCOMP_N_Q2_CH1_FGT pin.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.

If this tile is unused, you must connect the 499-Ω resistor between the GXF_RCOMP_P_Q2_CH1_FGT and GXF_RCOMP_N_Q2_CH1_FGT pin.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling case.

Tie to GND if these pins are not used.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling case.

Tie to GND if these pins are not used.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling input case.

Tie to GND or leave floating if this tile is not used.

AC or DC coupled.

Tie to GND if these pins are not used.

AC or DC coupled.

Tie to GND if these pins are not used.

1.8-V LVCMOS reset input in PCIe case.

In a PCIe* adapter card implementation, connect this signal from the PCIe* edge connector to each F-tile PCIe* reset input pin. Use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe* connector to the 1.8-V input of each F-tile transceiver that is used on the board. Provide a 1.8-V pull-up resistor as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3-V PCIe* nPERST signal on the adapter card.

If the F-tile is unused, tie to GND.

In case one reset pin controls multiple PCIe* IPs in bifurcation mode, ensure that this signal is de-asserted high after all IPs reference clocks are stable.

Connect VCC_HSSI_GXR to a 0.9-V low noise switching regulator. Refer to platform design guide for decoupling capacitor requirement.

Connect to GND if not used.

Connect VCCH_GXR to a 1.8-V low noise switching regulator. This voltage rail can be shared with VCCPT using proper isolation filtering.

To minimize regulator switching noise impact on channel jitter performance, keep the regulator switching frequency below 1 MHz. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Connect to GND if not used.

Connect VCCED_GXR to a dedicated 0.9-V linear regulator or low noise switching regulator. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Connect to GND if not used.

Connect VCCRT_GXR to a dedicated 1.0-V linear regulator or low noise switching regulator with filter. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for fitter details and decoupling capacitor requirement.

This analog supply cannot be shared.

Connect to GND if not used.

Connect VCCE_DTS_GXR to the same regulator as VCCE_PLL_GXR. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for fitter details and decoupling capacitor requirement.

Connect to GND when not used.

Connect VCCE_PLL_GXR to the same regulator as VCCE_DTS_GXR. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for fitter details and decoupling capacitor requirement.

Connect to GND when not used.

Connect VCCHFUSE_GXR to a dedicated 1.0-V linear or low noise switching regulator.

VCCHFUSE_GXR must be powered up even when the R-tile transceivers are not used. For more details about the decoupling recommendations for this voltage rail, refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines.

Connect to GND when not used.

Connect VCCCLK_GXR to a 1.0-V low noise switching regulator.

VCCCLK_GXR can share through ferrite bead. Refer to AN 910: Intel Agilex Power Distribution Network Design Guidelines for decoupling capacitor requirement.

Connect to GND when not used.

Connect a 150-ohm 1% resistor between the GXR_RCOMP_N_0 pin and GXR_RCOMP_P_0 pin of each R-tile bank.

RCOMP_P + RCOMP_N total trace routing (package and board) resistance is less than 0.500 ohms.

Recommend shielding by VSS.

In the PCB layout, do not route traces next to high speed clock/data aggressors. You are required to keep the maximum capacitance on RCOMP_P less than 5.0 pF.

If this tile is unused, leave these pins floating.

In a PCIe adapter card implementation, connect the PCIe nPERST signal from the PCIe edge connector to each R-tile transceiver bank I_PIN_PERST_N input.

Use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe connector to the 1.0-V I_PIN_PERST_N input of each R-tile transceiver that is used on the board.

Provide a 1.0-V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe connector is an open-drain signal. You must pull up the 3.3-V PCIe nPERST signal on the adapter card.

If the tile is unused, tie to GND.

In cases where two independent clock sources are used for 2x8 bifurcation mode, ensure that I_PIN_PERST_N is de-asserted high after both reference clocks are stable.

It supports HCSL I/O standard only, must be DC coupled.

You must connect a 100-MHz +/-100ppm reference clock to both reference clock inputs for x16 and 4x4 modes. These reference clocks must be derived from the same clock source. A fan-out buffer can be used but must meet a ± 100ppm requirement for Gen 5.

For 2x8 modes, you can connect both reference clock inputs to the same clock source or connect to two independent clock sources.

Leave these pins floating if unused.

Transceiver receiver pins, specific to the R-tile transceivers on the left (L) side or right (R) side of the device.

For PCIe Gen 5 mode, use the lower 16 bits [15:0]. These pins also support NRZ encoding up to 32 Gbps.

Transceiver transmitter pins, specific to the R-tile transceivers on the left (L) side or right (R) side of the device.

For PCIe Gen 5 mode, use the lower 16 bits [15:0]. These pins also support NRZ encoding up to 32 Gbps.

Transmitter pins must be AC coupled.

Leave these pins floating if unused.

For the range of the VCCL_HPS power supply voltage, refer to the Intel^® Agilex™ Device Data Sheet.

VID or standalone 0.95 (performance boost option)

VCCL_HPS can be shared with VCC if they are at the same VID voltage level.

If you do not intend to utilize the HPS in the Intel^® Agilex™ device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS floating or connected to GND.

Connect these pins to 1.8-V power supply. You have the option to source VCCIO_HPS pins from the same regulator as VCCIO_SDM.

If you do not intend to utilize the HPS in the Intel^® Agilex™ device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS floating or connected to GND.

Connect these pins to a 1.8-V power supply. You have the option to share VCCPLL_HPS with the same regulator as VCCPLL_SDM.

If you do not intend to utilize the HPS in the Intel^® Agilex™ device, you must still provide power to the HPS power supply. Do not leave the VCCPLL_HPS floating or connected to GND.

Connect this to the VCCL_HPS with proper isolation filtering.

If you do not intend to utilize the HPS in the Intel^® Agilex™ device, you must still provide power to the HPS power supply. Do not leave the VCCPLLDIG_HPS floating or connected to GND.

Clock input pin that drives the main PLL.

Connect a single-ended clock source to this pin. The I/O standard of the clock source must be compatible with VCCIO_HPS.

HPS JTAG test clock input pin.

Connect this pin through a 1-kΩ – 10-kΩ pull-down resistor to GND. Do not drive voltage higher than the VCCIO_HPS supply.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

HPS JTAG test mode select input pin.

Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

HPS JTAG test data output pin.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

HPS JTAG test data input pin.

Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply.

You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG.

General purpose input output.

Ensure that the I/O standard used is compatible with VCCIO_HPS.

HPS_IOA_[1..24]

HPS_IOB_[1..24]

SDMMC command line.

Pull this pin high on the board with a weak pull-up resistor. For example, a 10-kΩ to VCCIO_HPS.

SDMMC Data 3

When using SD card, there is an existing 50-kΩ pull-up on SDMMC Data Bit 3 which can be disabled in the HPS software by using the SET_CLR_CARD_DETECT (ACMD42) command. This is not applicable to the eMMC flash.

NAND Write Enable.

This is an active-low signal.

NAND Read Enable.

This is an active-low signal.

NAND Ready/Busy.

Connect this pin through a 1-kΩ to 10-kΩ pull-up resistor to VCCIO_HPS.

NAND Chip Enable.

This is an active-low signal.

SPIM0 Slave Select 0

This is an active-low signal.

SPIM0 Slave Select 1

This is an active-low signal.

SPIM1 Slave Select 0

This is an active-low signal.

SPIM1 Slave Select 1

This is an active-low signal.

SPIS0 Slave Select 0

This is an active-low signal.

SPIS1 Slave Select 0

This is an active-low signal.

UART0 Clear to Send

This is an active-low signal.

UART0 Request to Send

This is an active-low signal.

UART1 Clear to Send

This is an active-low signal.

UART1 Request to Send

This is an active-low signal.

Connect the VCCH to a dedicated 0.9-V power supply.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCL_SDM to a dedicated 0.8-V power supply.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCH_GXE to a dedicated 1.1-V power supply.

Connect the VCCCLK_GXE to a dedicated 2.5-V power supply.

Connect VCCPT to a dedicated 1.8-V power supply. Connect VCCADC, VCCPLL_SDM, VCCPLL_HPS, and VCCCLK_GXP to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Agilex™ devices. If you do not intend to utilize the HPS in the Intel^® Agilex™ device, you must still provide power to the HPS power supply pins.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCR_CORE to 1.2-V power supply.

Connect VCCIO_PIO and VCCIO_PIO_SDM to dedicated 1.2-V power supply.

Connect VCCA_PLL to the VCCR_CORE, VCCIO_PIO, and VCCIO_PIO_SDM supplies with proper isolation filtering.

If you do not intend to utilize the HPS in the Intel^® Agilex™ device, you must still provide power to these power supply pins. Do not leave the VCCIO_HPS power supply pins floating or connected to GND.

A 1.8-V power supply is required on this pin if field-programming of the eFuses is required. If field-programming of the eFuses is not required, tie this pin to VCCPT or leave it unconnected (floating). Do not tie this pin to GND.

If field-programming of the eFuses is required, Intel^® recommends using an adjustable regulator set to 1.8-V output when programming the eFuses.

Connect the VCC_HSSI_GXF to a dedicated 0.8-V power supply.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect VCCPT to a dedicated 1.8-V power supply.

Connect VCCADC, VCCPLL_SDM, VCCPLL_HPS, VCCH_FGT_GXF, and VCCCLK_GXF to the same power plane with proper isolation filtering.

Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Agilex™ devices.

If you do not intend to utilize the HPS in the Intel^® Agilex™ device, you must still provide power to the HPS power supply pins.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect to a dedicated 1.2-V power supply.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

There are some exceptions for the following pins:

• Connect pins BN48, BV57, and BU54 to GND.
• DNU17 (pin AT19) and DNU18 (pin AP17) must be pulled up via a 10kΩ to VCCCLK_GXE.

Tie these pins to GND.

Connect the VCCR_CORE to 1.8-V power supply.

Connect VCCA_PLL to a 1.8-V low noise switching regulator. You have the option to source VCCA_PLL from the same regulator as VCCPT with proper isolation filtering. The VCCA_PLL rail must reside in Group 2 power rails.

Connect the VCCH to a dedicated 0.9-V power supply.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCL_SDM to a dedicated 0.8-V power supply.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCH_GXE to a dedicated 1.1-V power supply.

Connect the VCCCLK_GXE to a dedicated 2.5-V power supply.

Connect VCCPT to a dedicated 1.8-V power supply. Connect VCCADC, VCCPLL_SDM, VCCPLL_HPS, and VCCCLK_GXP to the same power plane with proper isolation filtering. Depending on the regulator capabilities, you have the option to share this supply with multiple Intel^® Agilex™ devices. If you do not intend to utilize the HPS in the Intel^® Agilex™ device, you must still provide power to the HPS power supply pins.

When implementing a filtered supply topology, you must consider the IR drop across the filter.

Connect the VCCR_CORE to 1.8-V power supply.

Connect VCCA_PLL to the VCCR_CORE supply with proper isolation filtering.

Connect VCCIO_PIO and VCCIO_PIO_SDM to dedicated 1.2-V power supply.

If you do not intend to utilize the HPS in the Intel^® Agilex™ device, you must still provide power to these power supply pins. Do not leave the VCCIO_HPS power supply pins floating or connected to GND.

A 1.8-V power supply is required on this pin if field-programming of the eFuses is required. If field-programming of the eFuses is not required, tie this pin to VCCPT or leave it unconnected (floating). Do not tie this pin to GND.

If field-programming of the eFuses is required, Intel^® recommends using an adjustable regulator set to 1.8-V output when programming the eFuses.