AN 886: Intel® Agilex™ Device Design Guidelines

ID 683634
Date 8/26/2022

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Document Table of Contents

2.3.1. Evaluate Available HPS IP

The HPS architecture integrates a wide set of peripherals that reduce board size and increase performance within a system. Before evaluating soft IP for the FPGA core, identify which HPS peripherals can be leveraged to save FPGA I/O:
  • EMACs
  • USB Controllers
  • I2C Conctrollers
  • UARTs
  • SPI Master Controllers
  • SPI Slave Controllers
  • GPIO Interfaces

For more information about evaluating the available HPS IP, refer to the Intel® Agilex™ Hard Processor System Technical Reference Manual.