AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents NAND Flash Interface Design Guidelines

GUIDELINE: Ensure that the selected NAND flash device is an 8- or 16-bit ONFI 1.0 compliant device.

The NAND flash controller in the HPS requires:
  • The external flash device is 8- or 16-bit ONFI 1.0 compliant
  • Supports x16 for mass storage usage
  • Single-level cell (SLC) or multi-level cell (MLC)
  • Only one ce# and rb# pin pair is available for the boot source. Up to three additional pairs are available for mass storage
  • Page size: 512 bytes, 2 KB, 4 KB or 8 KB
  • Pages per block: 32, 64, 128, 256, 384 or 512
  • Error correction code (ECC) sector size can be programmed to 512 bytes (for 4, 8 or 16 bit correction) or 1024 bytes (24-bit correction)

For more information about the NAND Flash Controller, refer to the NAND Flash Controller section in the Intel Agilex® 7 Hard Processor System Technical Reference Manual,