AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents
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5.1.6. HPS I/O Settings: Constraints and Drive Strengths

GUIDELINE: Ensure that you have correctly configured the I/O settings for the HPS Dedicated I/O.

The HPS pin location assignments are managed automatically when you generate the Platform Designer system containing the HPS. Likewise, timing and I/O constraints for the HPS EMIF interface are managed by the Intel Agilex® 7 External Memory Interfaces for HPS IP. You must manage the following I/O constraints for the HPS Dedicated I/O using the Intel® Quartus® Prime software in the same way as for FPGA I/O: drive strength, weak pull-up enables, input/output delay chain, and termination settings. For implementation details, refer to the Intel Agilex® 7 F-Series and I-Series HPS I/O Banks chapter in the Intel Agilex® 7 General-Purpose I/O User Guide: F-Series and I-Series. Any peripherals configured to use FPGA I/O must also be fully constrained, including pin locations, using the Intel® Quartus® Prime software.