1. Introduction to the Intel Agilex® 7 Device Design Guidelines
2. System Specification
3. Device Selection
4. Security Considerations
5. Design Entry
6. Board and Software Considerations
7. Design Implementation, Analysis, Optimization, and Verification
8. Debugging
9. Embedded Software Design Guidelines for Intel Agilex® 7 SoC FPGAs
5.1.1. Firewall Planning
5.1.2. Boot And Configuration Considerations
5.1.3. HPS Clocking and Reset Design Considerations
5.1.4. Reset Configuration
5.1.5. HPS Pin Multiplexing Design Considerations
5.1.6. HPS I/O Settings: Constraints and Drive Strengths
5.1.7. Design Guidelines for HPS Interfaces
5.1.8. Interfacing between the FPGA and HPS
5.1.9. Implementing the Intel Agilex® 7 HPS Component
7.1. Selecting a Synthesis Tool
7.2. Device Resource Utilization Reports
7.3. Intel® Quartus® Prime Messages
7.4. Timing Constraints and Analysis
7.5. Area and Timing Optimization
7.6. Preserving Performance and Reducing Compilation Time
7.7. Designing with Intel® Hyperflex™
7.8. Simulation
7.9. Power Analysis
7.10. Power Optimization
7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
9.1. Overview
9.2. Golden Hardware Reference Design (GHRD)
9.3. Define Software Requirements
9.4. Define Software Architecture
9.5. Selecting Software Tools
9.6. Choosing the Bootloader Software
9.7. Selecting an Operating System for Your Application
9.8. Assembling Your Software Development Platform for Linux*
9.9. Assembling your Software Development Platform for Partner OS or RTOS
9.10. Driver Considerations
9.11. Boot And Configuration Considerations
9.12. System Reset Considerations
9.13. Flash Considerations
9.14. Develop Application
9.15. Test and Validate
9.16. Embedded Software Design Guidelines Revision History
6.1.8.4.1. Optional Configuration Pins
Number | Done? | Checklist Item |
---|---|---|
1 | Plan the board design to support optional configuration pins as required. |
You can enable the following optional configuration pins:
- OSC_CLK_1—Must be connected to a 25 MHz, 100 MHz, or 125 MHz source if used.
- CONF_DONE
- INIT_DONE
- CVP_CONFDONE
- SEU_ERROR
- HPS_COLD_nRESET
- Direct to Factory Image
- nCATTRIP
Note: Intel Agilex® 7 devices use OSC_CLK_1 pin as the reference clock for transceiver calibration. You must provide a stable and free running clock input at this pin. For more guidance on configuration pins, refer to the Intel Agilex® 7 Device Family Pin Connection Guidelines.
nCATTRIP
The Catastrophic Trip (nCATTRIP) is an optional signal assignable to any unused SDM_IO pin. When enabled, the nCATTRIP signal asserts when core temperature is greater than 125° C.
Attention: When nCATTRIP asserts, you must immediately power down the FPGA to avoid permanent damage to the device.
To enable the nCATTRIP output, select "USE nCATTRIP output" in the Configuration PIN GUI and assign the appropriate SDM I/O from the pulldown menu.
Figure 13. nCATTRIP Configuration Pin
For more information about nCATTRIP and other optional configuration pins, refer to the Secure Device Manager (SDM) Optional Signal Pins section in Intel Agilex® 7 Device Family Pin Connection Guidelines and the Intel Agilex® 7 Power Management User Guide.
GUIDELINE: Ensure that you follow the pull-up recommendations for the nCATTRIP signal to avoid incorrect sampling before you configure your device.
nCATTRIP SDM_IO Assignment Options | Internal Pull-Up or Pull-Down | External Pull-Up Recommendation |
---|---|---|
1-7, 9-15 | 20kΩ pull-up | Not required |
0, 8, 16 | 20kΩ pull-down | Connect 4.7kΩ to VCCIO_SDM |