1. Introduction to the Intel Agilex® 7 Device Design Guidelines
2. System Specification
3. Device Selection
4. Security Considerations
5. Design Entry
6. Board and Software Considerations
7. Design Implementation, Analysis, Optimization, and Verification
8. Debugging
9. Embedded Software Design Guidelines for Intel Agilex® 7 SoC FPGAs
5.1.1. Firewall Planning
5.1.2. Boot And Configuration Considerations
5.1.3. HPS Clocking and Reset Design Considerations
5.1.4. Reset Configuration
5.1.5. HPS Pin Multiplexing Design Considerations
5.1.6. HPS I/O Settings: Constraints and Drive Strengths
5.1.7. Design Guidelines for HPS Interfaces
5.1.8. Interfacing between the FPGA and HPS
5.1.9. Implementing the Intel Agilex® 7 HPS Component
5.1.7.1. Design Considerations for Selecting PHY Interfaces
5.1.7.2. USB Interface Design Guidelines
5.1.7.3. SD/MMC and eMMC Card Interface Design Guidelines
5.1.7.4. Design Guidelines for Flash Interfaces
5.1.7.5. UART Interface Design Guidelines
5.1.7.6. I2C Interface Design Guidelines
GUIDELINE: Instantiate the pseudo open-drain buffer when routing I2C signals through the FPGA fabric.
GUIDELINE: Ensure that the pull-ups are added to the external SDA and SCL signals in the board design.
GUIDELINE: Ensure that the high and low clock counts are configured correctly for the speed of the I2C interface
7.1. Selecting a Synthesis Tool
7.2. Device Resource Utilization Reports
7.3. Intel® Quartus® Prime Messages
7.4. Timing Constraints and Analysis
7.5. Area and Timing Optimization
7.6. Preserving Performance and Reducing Compilation Time
7.7. Designing with Intel® Hyperflex™
7.8. Simulation
7.9. Power Analysis
7.10. Power Optimization
7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
9.1. Overview
9.2. Golden Hardware Reference Design (GHRD)
9.3. Define Software Requirements
9.4. Define Software Architecture
9.5. Selecting Software Tools
9.6. Choosing the Bootloader Software
9.7. Selecting an Operating System for Your Application
9.8. Assembling Your Software Development Platform for Linux*
9.9. Assembling your Software Development Platform for Partner OS or RTOS
9.10. Driver Considerations
9.11. Boot And Configuration Considerations
9.12. System Reset Considerations
9.13. Flash Considerations
9.14. Develop Application
9.15. Test and Validate
9.16. Embedded Software Design Guidelines Revision History
5.1.7.6. I2C Interface Design Guidelines
GUIDELINE: Instantiate the pseudo open-drain buffer when routing I2C signals through the FPGA fabric.
When routing I2C signals through the FPGA, note that the I2C pins from the HPS to the FPGA fabric (i2c*_out_data, i2c*_out_clk) are not open-drain and are logic level inverted. Thus, to drive a logic level zero onto the I2C bus, drive the corresponding pin high. This implementation is useful as they can be used to tie to an output enable of a tri-state buffer directly. You must use the altiobuff to implement the open-drain buffer.
Intel recommends that you use I/O Buffer (ALTIOBUF) IP core when you expose I2C to FPGA fabric.
GUIDELINE: Ensure that the pull-ups are added to the external SDA and SCL signals in the board design.
Because the I2C signals are open drain, pull-ups are required to make sure that the bus is pulled high when no device on the bus is pulling it low.
Figure 6. I2C Wiring to FPGA pins
GUIDELINE: Ensure that the high and low clock counts are configured correctly for the speed of the I2C interface
There is an I2C internal clock located in the:
- SDM—125 MHz
- HPS—100 MHz