1. Introduction to the Intel Agilex® 7 Device Design Guidelines
2. System Specification
3. Device Selection
4. Security Considerations
5. Design Entry
6. Board and Software Considerations
7. Design Implementation, Analysis, Optimization, and Verification
8. Debugging
9. Embedded Software Design Guidelines for Intel Agilex® 7 SoC FPGAs
5.1.1. Firewall Planning
5.1.2. Boot And Configuration Considerations
5.1.3. HPS Clocking and Reset Design Considerations
5.1.4. Reset Configuration
5.1.5. HPS Pin Multiplexing Design Considerations
5.1.6. HPS I/O Settings: Constraints and Drive Strengths
5.1.7. Design Guidelines for HPS Interfaces
5.1.8. Interfacing between the FPGA and HPS
5.1.9. Implementing the Intel Agilex® 7 HPS Component
7.1. Selecting a Synthesis Tool
7.2. Device Resource Utilization Reports
7.3. Intel® Quartus® Prime Messages
7.4. Timing Constraints and Analysis
7.5. Area and Timing Optimization
7.6. Preserving Performance and Reducing Compilation Time
7.7. Designing with Intel® Hyperflex™
7.8. Simulation
7.9. Power Analysis
7.10. Power Optimization
7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
9.1. Overview
9.2. Golden Hardware Reference Design (GHRD)
9.3. Define Software Requirements
9.4. Define Software Architecture
9.5. Selecting Software Tools
9.6. Choosing the Bootloader Software
9.7. Selecting an Operating System for Your Application
9.8. Assembling Your Software Development Platform for Linux*
9.9. Assembling your Software Development Platform for Partner OS or RTOS
9.10. Driver Considerations
9.11. Boot And Configuration Considerations
9.12. System Reset Considerations
9.13. Flash Considerations
9.14. Develop Application
9.15. Test and Validate
9.16. Embedded Software Design Guidelines Revision History
6.1.8.5.4. MSEL Configuration Mode Pins
Number | Done? | Checklist Item |
---|---|---|
1 | Connect the SDM pins with MSEL function to select the configuration scheme; do not leave them floating. Pull the pins high or low through pull-up/down resistors. Do not hardwire the pins directly to VCCIO_SDM or GND. |
Select the configuration scheme by pulling the SDM pins with MSEL function high or low with external resistors. JTAG configuration is always available, regardless of the MSEL settings. The SDM pins with MSEL function are powered by the VCCIO_SDM power supply, and they have internal weak pull-up resistors.
During POR and reconfiguration, the SDM pins with MSEL function must be at LVTTL VIL and VIH levels to be considered as logic low and logic high, respectively. The SDM pins used for MSEL function also have other configuration functions, depending on the configuration schemes used. Do not hardwire the SDM pins with MSEL function to VCCIO_SDM or GND without pull-up or pull-down resistors.