AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents Signal Integrity

GUIDELINE: Make use of the SoC device’s On-Chip Termination (OCT).

Intel Agilex® 7 devices can tune their outputs to many settings, with 50 ohm output impedance often being the best value. Intel® Quartus® Prime automatically uses series OCT without calibration on RGMII outputs. Check the Intel® Quartus® Prime fitter report to verify the OCT settings on the interface’s outputs.

GUIDELINE: Use appropriate board-level termination on PHY outputs.

Only a few PHYs offer I/O tuning for their outputs, so Intel® recommends that you verify the signal path to the Intel Agilex® 7 device with a simulator. Place a series resistor on each signal near the PHY output pins to reduce the reflections if necessary.

GUIDELINE: Ensure reflections at PHY TX_CLK and EMAC RX_CLK inputs are minimized to prevent double-clocking.

Be cognizant if the connection is routed as a “T” as signal integrity must be maintained such that no double-edges are seen at REF_CLK loads. Ensure reflections at REF_CLK loads are minimized to prevent double-clocking.

GUIDELINE: Use a Signal Integrity (SI) simulation tool.

It is simple to run SI simulations on these unidirectional signals. These signals are almost always point-to-point, so simply determining an appropriate series resistor to place on each signal is usually sufficient. Many times, this resistor is not necessary, but study the device drive strength and trace lengths, as well as, topology when making this determination.