AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents

5.4.1. Memory Interfaces

Table 40.  Memory Interfaces Checklist
Number Done? Checklist Item
1   Use the External Memory Interfaces Intel Agilex® 7 core for each memory interface, and follow connection guidelines and restrictions in Intel Agilex® 7 FPGA External Memory Interface Overview and the External Memory Interfaces IP - Support Center web page.
2   For a given bank, most memory pins are tied to a dedicated location. Refer to the Intel Agilex® 7 Device Family Pin Connection Guidelines and External Memory Interface Pin Information for Intel Agilex® 7 F-Series and I-Series FPGAs for pin assignments.

Intel Agilex® 7 devices provide an efficient architecture to quickly and easily fit wide external memory interfaces with their small modular I/O banks. The Intel Agilex® 7 FPGA can support DDR external memory on any I/O banks on all sides of the device that do not support transceivers.

The self-calibrating External Memory Interfaces IP core is optimized to take advantage of the Intel Agilex® 7 I/O structure. The External Memory Interfaces IP core allows you to set external memory interface features and helps set up the physical interface (PHY) best suited for your system. When you use the Intel memory controller Intel® FPGA IP functions, the External Memory Interfaces IP core is instantiated automatically. If you design multiple memory interfaces into the device using Intel FPGA IP core, generate a unique interface for each instance to ensure good results instead of designing it once and instantiating it multiple times.

The data strobe DQS and data DQ pin locations are fixed in Intel Agilex® 7 devices. Before you design your device pin-out, refer to the memory interface guidelines in the Intel Agilex® 7 FPGA External Memory Interface Overview for details and important restrictions related to the connections for these and other memory-related signals.

You can implement a protocol that is not supported by External Memory Interfaces IP core by using the PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP core.

Address and command pins within the address/command bank must follow a fixed pin-out scheme, as defined in the <variation_name>_readme.txt file generated with your IP core. The pin-out scheme varies according to the topology of the memory interface. The pin-out scheme is a hardware requirement that you must follow. Some schemes require three lanes to implement address and command pins, while others require four lanes.