AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents

5.2.1. Clocking and Reset Design Considerations

You must follow the configuration clocking guidelines detailed in the Intel Agilex® 7 Configuration User Guide to ensure proper operation. The continual increases in clock frequency, device size, and design complexity now necessitate a well-thought out reset strategy that considers the possible effects of slight differences in the release from reset. This reset strategy must hold the device in reset until all registers and core logic are in user mode. Intel® strongly recommends that you use the nINIT_DONE signal from the Reset Release Intel Agilex® 7 FPGA IP. This output is one of the initial inputs to your reset circuit. For more information, refer to Intel Agilex® 7 Configuration User Guide.