AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 6/28/2023
Public
Document Table of Contents

6.4. Board Considerations Revision History

Table 85.  Board Considerations Revision History
Document Version Changes
2023.04.10
  • Updated product family name to "Intel Agilex® 7"
  • Added checklist item for power up/down sequence considerations
  • Added dual purpose pins to the Dual Purpose Configuration Pins section
2022.04.15 Updated the Device Power-Up section due to the change for the VCCBAT connection guideline.
2022.01.07
  • Updated the SmartVID section with the following:
    • Added a link to the Intel Agilex Power Management User Guide
    • Added the recommendation to use one of the VRs in the drop down menu to ensure that the system is using a VR that is fully tested and supported.
2021.10.29 Added guidelines for I/O pins during power-up or power-down.
2021.03.12
  • Changed the title for the Early Power Estimator (EPE) section to Intel® FPGA Power and Thermal Calculator .
  • Changed the Early Power Estimator (EPE) tool name to Intel® FPGA Power and Thermal Calculator.
2021.01.22 Added a link to the Board Developer Center web page in the "High-Speed Board Design Checklist" table.
2020.12.14 Added a new checklist item to specify that the SDM must fully control the QSPI reset in the Planning for Device Configuration section.
2020.09.15 Added a new guideline, "Connection Guidelines for Unused HPS Block", to the Unused Pins section.
2020.06.22
  • Added restrictions when using AVSTx16 or x32 configuration scheme:
    • Configuration Scheme Selection—Added a warning about using the AVSTx16 or x32 configuration scheme
    • Dual Purpose Configuration Pins—Removed AVST_READY
  • Clarified nCONFIG operation:
    • Updated Planning for Device Configuration
    • Added Device Power Cycling and Reconfiguration
2019.09.30 Initial release

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