AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents
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5.1.8. Interfacing between the FPGA and HPS

The memory-mapped connectivity between the HPS and the FPGA fabric is a crucial tool to maximize the performance of your design. Use the guidelines in this chapter for recommended topologies to optimize the performance of your system.

For more information, refer to the F2H Restrictions chapter in the Intel Agilex® 7 Hard Processor System Technical Reference Manual.