AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 5/12/2023
Document Table of Contents

9.11.4. Selecting HPS Boot Options

You must select a configuration and boot mode from the "HPS Boot Source" sub-window located on the "FPGA Interfaces" tab in Intel® Quartus® Prime Pro Edition.

  • FPGA Configuration First: The SDM configures the FPGA core and all the periphery I/O before loading the FSBL into the HPS on-chip RAM and releasing the HPS from reset. If any errors exist during initial configuration, the HPS is not released from reset.
  • HPS First: The SDM only configures the I/O required for the HPS SDRAM, and then loads the FSBL into the HPS on-chip RAM before releasing the HPS from reset. The FPGA core, as well as the other unused I/O, remain unconfigured. The HPS configures the rest of the FPGA.

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