AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents

5.3.1. NoC Architecture Basics

Intel Agilex® 7 M-Series FPGAs have two independent high-bandwidth hard memory NoCs located along the top and bottom edge of the die to interface between customer logic and memory resources. AXI* 4 managers in the FPGA fabric generate read and write transaction requests which are transferred into the hard memory NoC through initiator bridges at the fabric edge. A high-speed network of switches carries these transaction requests horizontally to target bridges which transfer the transaction requests to memory resources in the periphery. Transaction responses follow the same network of bridges and switches in reverse. Additionally, each hard memory NoC has a PLL and SSM to provide clocking and configure the NoC.