1. Introduction to the Intel Agilex® 7 Device Design Guidelines
2. System Specification
3. Device Selection
4. Security Considerations
5. Design Entry
6. Board and Software Considerations
7. Design Implementation, Analysis, Optimization, and Verification
8. Debugging
9. Embedded Software Design Guidelines for Intel Agilex® 7 SoC FPGAs
5.1.1. Firewall Planning
5.1.2. Boot And Configuration Considerations
5.1.3. HPS Clocking and Reset Design Considerations
5.1.4. Reset Configuration
5.1.5. HPS Pin Multiplexing Design Considerations
5.1.6. HPS I/O Settings: Constraints and Drive Strengths
5.1.7. Design Guidelines for HPS Interfaces
5.1.8. Interfacing between the FPGA and HPS
5.1.9. Implementing the Intel Agilex® 7 HPS Component
7.1. Selecting a Synthesis Tool
7.2. Device Resource Utilization Reports
7.3. Intel® Quartus® Prime Messages
7.4. Timing Constraints and Analysis
7.5. Area and Timing Optimization
7.6. Preserving Performance and Reducing Compilation Time
7.7. Designing with Intel® Hyperflex™
7.8. Simulation
7.9. Power Analysis
7.10. Power Optimization
7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
9.1. Overview
9.2. Golden Hardware Reference Design (GHRD)
9.3. Define Software Requirements
9.4. Define Software Architecture
9.5. Selecting Software Tools
9.6. Choosing the Bootloader Software
9.7. Selecting an Operating System for Your Application
9.8. Assembling Your Software Development Platform for Linux*
9.9. Assembling your Software Development Platform for Partner OS or RTOS
9.10. Driver Considerations
9.11. Boot And Configuration Considerations
9.12. System Reset Considerations
9.13. Flash Considerations
9.14. Develop Application
9.15. Test and Validate
9.16. Embedded Software Design Guidelines Revision History
5.1.2.1. Selecting HPS Boot Options
The Intel Agilex® 7 SoC device supports two boot and configuration modes. When designing your system, you must choose one of the following boot modes for your application: HPS First or FPGA First:
- FPGA Configuration First: The SDM configures the FPGA core and all the periphery I/O before loading the FSBL into the HPS on-chip RAM and releasing the HPS from reset. If any errors exist during initial configuration, the HPS is not released from reset.
- HPS First: The SDM only configures the I/O required for the HPS EMIF, and then loads the FSBL into the HPS on-chip RAM before releasing the HPS from reset. The FPGA core, as well as the other I/O, remain unconfigured. The HPS configures the rest of the FPGA.
Note: Faster HPS boot times are possible using HPS First boot mode.
Select a configuration and boot mode by selecting Assignments > Device > Device and Pin Options > HPS/FPGA configuration order tab in Intel® Quartus® Prime Pro Edition.
HPS First and FPGA First Boot Considerations
Guideline: HPS First Boot Mode Utilizes Early I/O Release
Follow the guidelines in this document to properly design your board and the SoC device pin out for the HPS EMIF interface for Early I/O Release.
For more information about the supported boot modes, refer to the Intel Agilex® 7 SoC Boot User Guide and the "Boot and Configuration" section in the Intel Agilex® 7 Hard Processor System Technical Reference Manual.
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