AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents Overview of HPS Memory-Mapped Interfaces

The HPS exposes two memory-mapped HPS-to-FPGA interfaces:
  • HPS-to-FPGA bridge: 32-, 64-, or 128-bit wide Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* )-4
  • Lightweight HPS-to-FPGA bridge: 32-bit wide AXI-4
  • FPGA-to-HPS bridge: 128-, 256-, 512-bit wide ACE*-Lite
Figure 7.  Intel Agilex® 7 HPS Connectivity

Timing Closure Considerations

The bridges exposed to the FPGA are synchronous; and clock crossing is performed within the interface itself. As a result, you must only ensure that both the FPGA-facing logic and your design close timing in Timing Analyzer. Interrupts are considered asynchronous by the HPS, and as a result the HPS logic resynchronizes them to the internal HPS clock domain so there is no need to close timing for them.

GUIDELINE: Intel® recommends that you protect any area of the memory map which is not mapped to a slave, and also add protection against the possibility of non-reactive slaves.

  • Any memory mapped bus segment is protected by an IP defined as the default slave (if there are gaps): Platform Designer system view, right click to edit the default slave in the displayed column.
    • This routes accesses to areas not covered to this slave: This can be any slave, but an error slave or timeout slave make sense (as they return a slave error).
  • AXI timeout bridge:
    • Sits on the bus (pass through) and issues an AXI slave error to end a transaction in a valid way if a slave does not respond. This makes a perfect default slave.

In addition, ensure that all slaves and buses are reset cleanly if the FPGA logic, or the HPS are reset. This provides clean initialization and clearing of stale transactions in the Platform Designer created network interconnect.

  • Clock Reset IP:
    • Creates a reset signal once the FPGA enters user mode which can be used to synchronous reset all IP / buses
  • HPS reset output:
    • Can be used to reset IP and busses if the HPS has been reset (independent from the FPGA core logic).