22.214.171.124. UART Interface Design Guidelines
HPS boot firmware outputs console status messages throughout the boot process to the HPS UART port. If you want to view boot firmware console output, consider the following guidelines to assign the HPS UART peripheral to device I/O that are available at HPS boot time.
GUIDELINE: For the HPS First boot and configuration scheme, assign the HPS UART peripheral to the HPS Dedicated I/O Bank.
The SDM configures and releases to user-mode (Early I/O Release flow) the HPS Dedicated I/O and HPS EMIF I/O before booting the HPS. The remaining FPGA I/O and fabric are not available until the rest of the FPGA is configured at a later point in the boot flow.
GUIDELINE: For the FPGA First boot and configuration scheme, you can assign the HPS UART to either HPS Dedicated or FPGA I/O.
The SDM configures the entire FPGA portion, including the entire I/O ring before booting the HPS.
GUIDELINE: Properly connect flow control signals when routing the UART signals through the FPGA fabric.
For more information, refer to the "UART Controller" section in the Intel Agilex® 7 Hard Processor System Technical Reference Manual.
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