AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents

5.3.6. NoC Physical Placement

Use the Interface Planner tool in the Intel® Quartus® Prime software to create physical location assignments for NoC initiator bridges, target bridges, PLL, and SSM. For Intel Agilex® 7 M-Series devices, a NoC View is available within the Interface Planner tool to assist with initiator and target placement. Target bridges are generally fixed in location by their connection to HBM2e or external memory. Initiator bridges are not fixed and can be placed in several locations along the edge of the die. The placement of initiator bridges relative to the targets they connect to can impact whether the NoC can meet your performance targets.

Within the Interface Planner tool, the NoC Performance Report is available that performs a static analysis of your initiator and target bridge placements. This report estimates whether the bandwidth targets specified in the NoC Assignment Editor tool can be achieved with the current placement. It also reports the minimum structural latency for each initiator-target connection based on their relative placements.

The hard memory NoC is a series of interconnected switches that connect to the initiator and target bridges. The switches are connected by a network of high-speed links. There are separate links for carrying traffic left-to-right and for carrying traffic right-to-left. Additionally, there are separate links for transaction requests (including write data) and transaction responses (including read data). Having multiple initiator-target connections transferring the same type of data in the same direction can cause congestion on the hard memory NoC.

Many switches connect to both an initiator bridge and one or more target bridges. Connections between initiator bridges directly across from their target bridges do not utilize the horizontal high-speed links. Utilize these initiator bridge locations whenever possible to minimize congestion on the horizontal links.

Because the hard memory NoC has separate links for carrying left-to-right traffic and right-to-left traffic, consider placing additional initiator bridges so that some are to the left of their targets, and some are to the right.

Finally, the minimum latency through the hard memory NoC is directly related to how far apart initiator bridges and target bridges are placed. Placing initiators close to their targets results in reduced latency.

For more information about the NoC View and NoC Performance Report available within the Interface Planner tool, refer to the Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide.