AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents

6.1.8. Planning for Device Configuration

Table 57.  Planning for Device Configuration Checklist
Number Done? Checklist Item
1   Consider whether you require multiple configuration schemes.
2   Ensure that you have OSC_CLK_1 and REFCLK external clocks for Transceivers and CLK for EMIF.
3   Follow the configuration guidelines and additional clock requirements if your design is using PCIe, transceiver channels, HPS, High Bandwidth Memory (HBM2E) IP core, or SmartVID. Refer to the Intel Agilex® 7 Configuration User Guide and Intel Agilex® 7 Power Management User Guide for the guidelines.
4   Intel strongly recommends using the Intel Agilex® 7 Reset Release IP in your design to provide a known initialized state for your logic to begin operation. The Reset Release IP is available in the Intel® Quartus® Prime software version 19.1 and later. Refer to the Intel Agilex® 7 Configuration User Guide for the guidelines.
5   Ensure that nCONFIG is driven for passive configuration modes and pulled high for active configuration modes, and nSTATUS is monitored appropriately as described in the Intel Agilex® 7 Device Family Pin Connection Guidelines and Intel Agilex® 7 Configuration User Guide to enable reliable configuration.
6   Ensure that nCONFIG is not directly driven by FPGA, HPS I/Os, or any component that has dependency on FPGA or HPS I/Os.
7   If you use Active Serial x4 configuration mode, you must connect the serial flash or quad SPI flash reset pin to the AS_nRST pin. The SDM must fully control the QSPI reset. Do not connect the quad SPI reset pin to any external host.

Intel Agilex® 7 devices are based on SRAM cells. You must download configuration data to the Intel Agilex® 7 device each time the device powers up, because SRAM is volatile. Consider whether you require multiple configuration schemes, such as one for debugging or testing and another for the production environment.

Choosing the device configuration method early allows system and board designers to determine what companion devices, if any, are required for the system. Your board layout also depends on the configuration method you plan to use for the programmable device, because different schemes require different connections.

In addition, Intel Agilex® 7 devices offer advanced configuration features, depending on your configuration scheme. Intel Agilex® 7 devices also include optional configuration pins and a reconfiguration option that you choose early in the design process (and set up in the Intel® Quartus® Prime software), so you have all the information required for your board and system design.