AN 886: Intel Agilex® 7 Device Design Guidelines

ID 683634
Date 10/09/2023
Document Table of Contents
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5.1.3. HPS Clocking and Reset Design Considerations

The main clock and reset sources for the HPS are:
  • HPS_OSC_CLK device I/O pin—The external clock source for the HPS PLLs, which generate clocks for the MPU Subsystem, CCU, SMMU, L3 Interconnect, HPS peripherals and HPS-to-FPGA user clocks.
  • nCONFIG device I/O pin—nCONFIG is a dedicated input pin to the SDM that holds off initial configuration and initiates FPGA reconfiguration. An nCONFIG assertion cold resets the HPS.
  • HPS_COLD_nRESET device I/O pin—An optional reset input that cold resets only the HPS and is configured for bidirectional operation.

GUIDELINE: You can configure the HPS_COLD_nRESET pin to be on any open SDM I/O pin.

From Intel® Quartus® Prime,
  1. Click Assignments > Device.
  2. Click the "Device and Pin Options" button.
  3. Go to the "Configuration" tab.
  4. Click the "Configuration Pin Options" button.
  5. Click the "USE_HPS_COLD_nRESET" check box and select available SDM_IO pin.
For more information, refer to the “Pin Features and Connection for HPS Clocks, Reset and POR.” section.