7.4. Timing Constraints and Analysis
The Design Assistant automatically reports any violations against a standard set of Intel recommended design guidelines. Click Assignments > Settings > Design Assistant Rule Settings to enable this feature. The Design Assistant rules include Timing Closure, Clocking, CDC, reset and floor-planning. You can customize the Design Assistant for your design characteristics and reporting requirements.
|1||Ensure timing constraints are complete and accurate, including all clock signals and I/O delays.|
|2||Review the Timing Analyzer reports after compilation to ensure there are no timing violations.|
|3||Ensure that the input I/O times are not violated when data is provided to the Intel Agilex® 7 device.|
|4||Review the Design Assistant violations and address them if they are a concern to the current design.|
In an FPGA design flow, accurate timing constraints allow timing-driven synthesis software and place-and-route software to obtain optimal results. Timing constraints are critical to ensure designs meet their timing requirements, which represent actual design requirements that must be met for the device to operate correctly. The Intel® Quartus® Prime software optimizes and analyzes your design using different timing models for each device speed grade, so you must perform timing analysis for the correct speed grade. The final programmed device might not operate as expected if the timing paths are not fully constrained, analyzed, and verified to meet requirements.
The Intel® Quartus® Prime software includes the Intel® Quartus® Prime Timing Analyzer, a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design. It supports the industry standard Synopsys* Design Constraints (SDC) format timing constraints, and has an easy-to-use GUI with interactive timing reports. It is ideal for constraining high-speed source-synchronous interfaces and clock multiplexing design structures.
A comprehensive static timing analysis includes analysis of register to register, I/O, and asynchronous reset paths. It is important to specify the frequencies and relationships for all clocks in your design. Use input and output delay constraints to specify external device or board timing parameters. Specify accurate timing requirements for external interfacing components to reflect the exact system intent.
The Timing Analyzer performs static timing analysis on the entire system, using data required times, data arrival times, and clock arrival times to verify circuit performance and detect possible timing violations. It determines the timing relationships that must be met for the design to correctly function.
You can use the report_datasheet command to generate a datasheet report that summarizes the I/O timing characteristics of the entire design.
For more information about timing constraint, refer to Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer.