External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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5.3. Simulating the Design Example with Mentor Graphics* AXI4 Master BFM ( Intel® FPGA Edition)

The traffic generator in the EMIF design example sends traffic using the Avalon® memory-mapped interface.

This section describes how to modify the EMIF design example for a 64-bit DDR4 interface (with data mask enabled) to perform functional simulation using the Mentor Graphics* AXI4 Master Bus Functional Model (BFM) (Intel FPGA Edition) to write data and read data from the EMIF IP.

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