220.127.116.11. Maximum Number of Interfaces
Unless otherwise noted, the calculation for the maximum number of interfaces is based on independent interfaces where the address or command pins are not shared.
For interface information for Intel® Agilex™ devices, consult the EMIF Device Selector on www.intel.com.
Timing closure depends on device resource and routing utilization. For more information about timing closure, refer to the Area and Timing Optimization Techniques chapter in the Intel® Quartus® Prime Handbook.
Did you find the information on this page useful?