184.108.40.206. PHY or Core
Core timing analysis excludes user logic timing to or from EMIF blocks. The EMIF IP provides a constrained clock (for example: ddr4_usr_clk) with which to clock customer logic; pll_afi_clk serves this purpose.
The PHY or core analyzes this path by calling the report_timing command in <variation_name>_report_timing.tcl and <variation_name>_report_timing_core.tcl.
Did you find the information on this page useful?