External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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6.1.1. Intel Agilex EMIF IP DDR4 Parameters: General

Table 66.  Group: General / Interface
Display Name Description
Configuration Specifies the configuration of the memory interface. The available options depend on the protocol and the targeted FPGA product. (Identifier: PHY_DDR4_CONFIG_ENUM)
Use clamshell layout Specifies the use of a clamshell topology. When clamshell topology is used, the bottom memory chip should be wired with the address pins mirrored, in accordance with the JEDEC specification JESD21-C. Each rank requires two CS pins, such that the top and bottom memory chips can be configured separately.

For single-rank components:

For the top (non-mirrored) component, FPGA_CS0 goes to MEM_TOP_CS0

For the bottom (mirrored) component, FPGA_CS1 goes to MEM_BOT_CS0

For dual-rank components:

For the top (non-mirrored) components, FPGA_CS0 goes to MEM_TOP_CS0 and FPGA_CS1 goes to MEM_TOP_CS1

For the bottom (mirrored) components, FPGA_CS2 goes to MEM_BOT_CS0 and FPGA_CS3 goes to MEM_BOT_CS1

(Identifier: PHY_DDR4_USER_CLAMSHELL_EN)
Table 67.  Group: General / Clocks
Display Name Description
Memory clock frequency Specifies the operating frequency of the memory interface in MHz. If you change the memory frequency, you should update the memory latency parameters on the Memory tab and the memory timing parameters on the Mem Timing tab. (Identifier: PHY_DDR4_MEM_CLK_FREQ_MHZ)
Use recommended PLL reference clock frequency Specifies that the PLL reference clock frequency is automatically calculated for best performance. If you want to specify a different PLL reference clock frequency, uncheck the check box for this parameter. (Identifier: PHY_DDR4_DEFAULT_REF_CLK_FREQ)
PLL reference clock frequency This parameter tells the IP what PLL reference clock frequency you specify. You must select a valid PLL reference clock frequency from the list. The values in the list can change when the memory interface frequency or the clock rate of user logic changes. You should use the fastest possible PLL reference clock frequency because it leads to better jitter performance. Selection is required only if you do not check the "Use recommended PLL reference clock frequency" option. (Identifier: PHY_DDR4_USER_REF_CLK_FREQ_MHZ)
PLL reference clock jitter Specifies the peak-to-peak jitter on the PLL reference clock source. The clock source of the PLL reference clock must meet or exceed the following jitter requirements: 10ps peak to peak, or 1.42ps RMS at 1e-12 BER, 1.22ps at 1e-16 BER. (Identifier: PHY_DDR4_REF_CLK_JITTER_PS)
Clock rate of user logic Specifies the relationship between the user logic clock frequency and the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a quarter-rate interface means that the user logic in the FPGA runs at 200MHz. The list of available options is dependent on the memory protocol and device family. (Identifier: PHY_DDR4_RATE_ENUM)
Specify additional core clocks based on existing PLL Displays additional parameters allowing you to create additional output clocks based on the existing PLL. This parameter provides an alternative clock-generation mechanism for when your design exhausts available PLL resources. The additional output clocks that you create can be fed into the core. Clock signals created with this parameter are synchronous to each other, but asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains. (Identifier: PLL_ADD_EXTRA_CLKS)
Table 68.  Group: General / Mimic Hard Processor System (HPS) EMIF
Display Name Description
Mimic HPS EMIF This option generates an EMIF at the same tiles as HPS EMIF following the same rules as HPS EMIF. Use this option to generate a fabric EMIF that mimics HPS-EMIF restrictions. (Identifier: PHY_DDR4_MIMIC_HPS_EMIF)
Table 69.  Group: General / Clocks / Additional Core Clocks
Display Name Description
Number of additional core clocks Specifies the number of additional output clocks to create from the PLL. (Identifier: PLL_USER_NUM_OF_EXTRA_CLKS)
Table 70.  Group: General / Clocks / Additional Core Clocks / pll_extra_clk_0
Display Name Description
Frequency Specifies the frequency of the core clock signal. (Identifier: PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5)
Phase shift Specifies the phase shift of the core clock signal. (Identifier: PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5)
Table 71.  Group: General / Clocks / Additional Core Clocks / pll_extra_clk_1
Display Name Description
Frequency Specifies the frequency of the core clock signal. (Identifier: PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6)
Phase shift Specifies the phase shift of the core clock signal. (Identifier: PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6)
Table 72.  Group: General / Clocks / Additional Core Clocks / pll_extra_clk_2
Display Name Description
Frequency Specifies the frequency of the core clock signal. (Identifier: PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7)
Phase shift Specifies the phase shift of the core clock signal. (Identifier: PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7)
Table 73.  Group: General / Clocks / Additional Core Clocks / pll_extra_clk_3
Display Name Description
Frequency Specifies the frequency of the core clock signal. (Identifier: PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8)
Phase shift Specifies the phase shift of the core clock signal. (Identifier: PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8)

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