18.104.22.168. Resource Sharing Guidelines (Multiple Interfaces)
PLL Reference Clock Pin
To conserve pin usage and enable core clock network and I/O bank sharing, you can share a PLL reference clock pin between multiple external memory interfaces; the interfaces must be of the same protocol, rate, and frequency. Sharing of a PLL reference clock pin also implies sharing of the reference clock network.
Observe the following guidelines for sharing the PLL reference clock pin:
- To share a PLL reference clock pin, connect the same signal to the pll_ref_clk port of multiple external memory interfaces in the RTL code.
- Place related external memory interfaces in the same I/O column.
- Place related external memory interfaces in adjacent I/O banks. If you leave an unused I/O bank between the I/O banks used by the external memory interfaces, that I/O bank cannot be used by any other external memory interface with a different PLL reference clock signal.
To reduce I/O bank utilization, you may share an I/O Bank with other external memory interfaces.
Observe the following guidelines for sharing an I/O Bank:
- Related external memory interfaces must have the same protocol, rate, memory clock frequency, and PLL reference clock.
- You cannot use a given I/O bank as the address and command bank for more than one external memory interface.
- You cannot share an I/O lane between external memory interfaces. Also, any pin in the same bank that is not used by an external memory interface may not be available for use as a general purpose I/O pin.
- You cannot share sub-banks between external memory interfaces.
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