External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
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11.10.3.1.3. Parameter Table Arrays

This topic describes the structure of some arrays whose addresses are stored in the parameter table. These arrays are used during calibration and may be useful for debugging your design.

Cal Data Array (pt_CAL_DATA_PTR)

The Cal Data Array’s base address is equal to: (user_ram base address) + (offset for cal_data array, read from pt_CAL_DATA_PTR)

Table 174.  cal_data Array
Offset from Pointer Address Entry Size (bytes)
0x0 STARTING_VREFIN 4
0x4 CAL_TREFI 4
0x8 CAL_TRFC 4
0xC CAL_ADDR0 4
0x10 CAL_ADDR1 4

MR Array (pt_MR_PTR)

The MR Array’s base address is equal to: (user_ram base address) + (offset for MR array, read from pt_MR_PTR)

Each array element is 32 bits wide. There can be up to three types of information in this array, as follows:

  • Values to be written into Mode Registers. For ordering refer to ENUM_MR_INDEX. The number of entries of this type is pt_NUM_MR, and should be 0 for non-DDR protocols. Each entry is coded as 32 bits: {19'b0, A[12:0]} (Bank ADDR not included).
  • On RDIMM or LRDIMM, the data above is followed by 64 bit RDIMM configuration, comprising 16 control words of 4 bits each.
  • On LRDIMM, the data above is followed by (pt_NUM_LRDIMM_CFG * 3) number of bytes for extra LRDIMM configuration, each entry being 3 bytes of data with no padding bytes between triplets. Each triplet is defined as {func_sel, address, value}. For example, {3, 2, 6} means F3RC2=6 .

Pin Address Array (pt_PIN_ADDR_PTR)

Each array element is 8 bits wide. The order of the pins is as follows:

  1. All the pins in the appropriate ENUM_AC_ROM_* (based on the protocol used by this design) for command/address pins.
  2. All data pins in the following order, where each item in the brackets below can be a single bit, multi-bit bus (from LSB to MSB), or zero entry (non-existing bus):
    • DDR4: [DQS_T, DQS_C, DM, DQ]
    • QDR-IV: [QKA, QKB, QKA_N, QKB_N, DKA, DKB, DKA_N, DKB_N, DIVA, DIVB, DQA, DQB]

    For example:

    The following table depicts the pin address array for a DDR4 interface of x16 data width, split into two DQS groups:

    Table 175.  Example
    Section Address Element
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr = user_ram base address + pt_PIN_ADDR_PTR DDR4_CKE_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1 DDR4_CKE_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2 DDR4_CKE_2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x3 DDR4_CKE_3
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x4 DDR4_ODT_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x5 DDR4_ODT_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x6 DDR4_ODT_2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x7 DDR4_ODT_3
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x8 DDR4_RESET
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x9 DDR4_ACT
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xA DDR4_CS_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xB DDR4_CS_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xC DDR4_CS_2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xD DDR4_CS_3
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xE DDR4_C_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0xF DDR4_C_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x10 DDR4_C_2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x11 DDR4_BA_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x12 DDR4_BA_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x13 DDR4_BG_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x14 DDR4_BG_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x15 DDR4_ADD_0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x16 DDR4_ADD_1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x17 DDR4_ADD_2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x18 DDR4_ADD_3
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x19 DDR4_ADD_4
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1A DDR4_ADD_5
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1B DDR4_ADD_6
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1C DDR4_ADD_7
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1D DDR4_ADD_8
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1E DDR4_ADD_9
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x1F DDR4_ADD_10
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x20 DDR4_ADD_11
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x21 DDR4_ADD_12
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x22 DDR4_ADD_13
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x23 DDR4_ADD_14
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x24 DDR4_ADD_15
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x25 DDR4_ADD_16
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x26 DDR4_ADD_17
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x27 DDR4_ADD_18
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x28 DDR4_ADD_19
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x29 DDR4_PAR_IN
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2A REAL_AC_PIN_DDR4_NUM
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2A DDR4_RDATA_EN
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2B DDR4_MRNK_RD
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2C DDR4_WDATA_VALID
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2D DDR4_MRNK_WRT
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2E AC_DDR4_NUM
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2A DDR4_ALERT0_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2B DDR4_ALERT1_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2C DDR4_CK0
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2D DDR4_CK0_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2E DDR4_CK1
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x2F DDR4_CK1_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x30 DDR4_CK2
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x31 DDR4_CK2_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x32 DDR4_CK3
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x33 DDR4_CK3_N
    1 (ENUM_AC_ROM_DDR4) Pin Address Array Base Addr + 0x34 AC_PIN_DDR4_NUM
    2 (DQS_T) Pin Address Array Base Addr + 0x35 DQS_0
    2 (DQS_T) Pin Address Array Base Addr + 0x36 DQS_1
    2 (DQS_C) Pin Address Array Base Addr + 0x37 DQS_N_0
    2 (DQS_C) Pin Address Array Base Addr + 0x38 DQS_N_1
    2 (DM) Pin Address Array Base Addr + 0x39 DM_0
    2 (DM) Pin Address Array Base Addr + 0x40 DM_1
    2 (DQ) Pin Address Array Base Addr + 0x41 DQ_0
    2 (DQ) Pin Address Array Base Addr + 0x42 DQ_1
    2 (DQ) Pin Address Array Base Addr + 0x43 DQ_2
    2 (DQ) Pin Address Array Base Addr + 0x44 DQ_3
    2 (DQ) Pin Address Array Base Addr + 0x45 DQ_4
    2 (DQ) Pin Address Array Base Addr + 0x46 DQ_5
    2 (DQ) Pin Address Array Base Addr + 0x47 DQ_6
    2 (DQ) Pin Address Array Base Addr + 0x48 DQ_7
    2 (DQ) Pin Address Array Base Addr + 0x49 DQ_8
    2 (DQ) Pin Address Array Base Addr + 0x50 DQ_9
    2 (DQ) Pin Address Array Base Addr + 0x51 DQ_10
    2 (DQ) Pin Address Array Base Addr + 0x52 DQ_11
    2 (DQ) Pin Address Array Base Addr + 0x53 DQ_12
    2 (DQ) Pin Address Array Base Addr + 0x54 DQ_13
    2 (DQ) Pin Address Array Base Addr + 0x55 DQ_14
    2 (DQ) Pin Address Array Base Addr + 0x56 DQ_15

    In most cases, each entry is encoded as 8 bits: {lane-index[3:0], pin-index[3:0]}, where lane-index is the index to the lane addresses in pt_TILE_ID_PTR and pin-index is the physical pin index in that lane.

    16-bit encoding is used when the number of data groups exceeds 16, so 4 bits are insufficient. 16-bit encoding is also used for CA pins such as alert_n, which are not necessarily physically located in a CA lane. If an alert_n pin is placed in a data lane, the absolute tile-id value is used: {1'b0, data-lane-index[6:0], pin-index[3:0], 4'b1111}, where data-lane-index is similar to lane-index in 8-bit encoding, except that it is always based off data lanes, regardless of pin types. For 16-bit code, the LSB byte appears first, followed by the MSB byte.

    The lane-index is based off of the corresponding group, specifically either the CA lanes or the data lanes. (For an explanation of CA lanes and data lanes, refer to the comments of pt_TILE_ID_PTR, above).

    For example:

    In a DDR4 interface, the array element for DQ_0 = 8’b0001_0010

    lane_index = 4’b0001

    pin_index = 4’b0010

    Because this is a data pin, you should refer to index 1 in DATA_LANES (that is, “DATA_LANES: TILE ID 1” in Tile ID Array ) to get the actual tile and lane location for DQ0 data pin for this interface.

    The unused slots (such as CKE_3 when there are only 2 CKE pins in the design) must be filled with 8'b0.

Tile ID Array (pt_TILE_ID_PTR)

Each array element is an 8-bit-wide tile-id: {tile-pos[4:0], lane-id[2:0]}. This array contains tile IDs of three groups, in the following order:

  1. Centers.
  2. CA lanes.
  3. Data lanes.

pt_NUM_CENTERS, pt_NUM_CA_LANES, and pt_NUM_DATA_LANES indicate how many tile IDs exist in Centers, CA lanes, and Data lanes respectively.

The table below depicts the Tile ID Array for an example with the following characteristics:

  • pt_NUM_CENTERS = 0x03
  • pt_NUM_CA_LANES = 0x03
  • pt_NUM_DATA_LANES = 0x09
Table 176.  Tile ID Array Example
Address Group Element
Base Address for Tile ID Array = user-ram base address + pt_TILE_ID_PTR offset CENTERS CENTERS: Tile ID 0
Base Address for Tile ID Array + 0x1 CENTERS CENTERS: Tile ID 1
Base Address for Tile ID Array + 0x2 CENTERS CENTERS: Tile ID 2
Base Address for Tile ID Array + 0x3 CA_LANES CA_LANES: Tile ID 0
Base Address for Tile ID Array + 0x4 CA_LANES CA_LANES: Tile ID 1
Base Address for Tile ID Array + 0x5 CA_LANES CA_LANES: Tile ID 2
Base Address for Tile ID Array + 0x6 DATA_LANES DATA_LANES: TILE ID 0
Base Address for Tile ID Array + 0x7 DATA_LANES DATA_LANES: TILE ID 1
Base Address for Tile ID Array + 0x8 DATA_LANES DATA_LANES: TILE ID 2
Base Address for Tile ID Array + 0x9 DATA_LANES DATA_LANES: TILE ID 3
Base Address for Tile ID Array + 0xA DATA_LANES DATA_LANES: TILE ID 4
Base Address for Tile ID Array + 0xB DATA_LANES DATA_LANES: TILE ID 5
Base Address for Tile ID Array + 0xC DATA_LANES DATA_LANES: TILE ID 6
Base Address for Tile ID Array + 0xD DATA_LANES DATA_LANES: TILE ID 7
Base Address for Tile ID Array + 0xE DATA_LANES DATA_LANES: TILE ID 8

The order of lanes inside each group is arbitrary, except that the first address must be the center address with an active sequencer.

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