External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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4.1.1.23. hps_emif for DDR4

Conduit between Hard Processor Subsystem and memory interface
Table 36.  Interface: hps_emifInterface type: Conduit
Port Name Direction Description
hps_to_emif Input Signals coming from Hard Processor Subsystem to the memory interface
emif_to_hps Output Signals going to Hard Processor Subsystem from the memory interface
hps_to_emif_gp Input Signals coming from Hard Processor Subsystem GPIO to the memory interface
emif_to_hps_gp Output Signals going to Hard Processor Subsystem GPIO from the memory interface

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