External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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Document Table of Contents

13. Document Revision History for External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

Document version Intel® Quartus® Prime Version IP Version Changes
2022.06.20 22.2 2.6.1
  • In the Architecture chapter:
    • Added sub-bank ordering figures in the I/O Bank topic.
    • Added rows to the tables in the Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme topic.
  • In the Simulation chapter, added the Simulating the Design Example with Mentor Graphics* AXI4 Master BFM (Intel FPGA Edition) section.
  • In the DDR4 chapter, modified the tables in the Skew Matching Guidelines for DDR4 DIMM Configurations and Skew Matching Guidelines for DDR4 Discrete Configurations topics.
  • In the QDR-IV chapter, modified the table in the Skew Matching Guidelines for QDR-IV Configurations topic.
2022.03.28 22.1 2.6.1
  • In the Architecture chapter:
    • Inserted a new step 1 in the Guidelines for Debugging Calibration Issues topic.
    • Added Using a Custom Controller with the Hard PHY topic.
  • In the Simulating Memory IP chapter, added an Abstract I/O SSM section to the Simulation Options topic.
  • In the Board Design Guidelines section of the DDR4 chapter, modified the figure and the second bullet point in the Intel® Agilex™ EMIF -Specific Routing Guidelines for Various DDR4 Topologies topic.
  • In the Board Design Guidelnes section of the QDR-IV chapter:
    • Added an additional figure and associated text to the Reference Stackup topic.
    • Added a reference to related information following the table in the QDR-IV Single Device Memory Topology topic.
    • Modified one row and added one row to the table in the Skew Matching Guidelines for QDR-IV Configurations topic.
  • In the Intel® Agilex™ FPGA EMIF IP - I/O Timing Closure chapter, added the Understanding the *_ip_parameters.dat File and Making a Mask Polygon topic.
  • In the Debugging chapter:
    • Added the Memory Timing Parameter Evaluation and Verify that the Board Has the Correct Memory Component or DIMM Installed topics to the Categorizing Hardware Issues section.
    • Inserted a new step 1 in the Guidelines for Debugging Calibration Issues topic.
2022.01.31 21.4 2.6.0
  • In the Using the Configurable Traffic Generator (TG2) section of the Debugging chapter:
    • Modified the table in the Configuration and Status Registers topic.
    • Modified the last dialog box image and description in the Address Pattern Examples - Basic Mode topic.
2021.12.13 21.4 2.6.0
  • In the Product Architecture chapter:
    • Added PHY-Only Mode to the Introduction topic.
    • In the I/O Banks topic, modified the first sentence of the short paragraph preceding the Zipper Block section, and the last sentence of the first paragraph in the I/O Sub-Bank Usage section.
    • Removed a note from the User-requested Reset in Intel® Agilex™ EMIF IP topic.
  • In the End-User Signals chapter, added the AFI Signals and AFI 4.0 Timing Diagrams sections.
  • In the DDR4 chapter:
    • In the Intel Agilex EMIF IP DDR4 Parameters: Memory topic, added notes about custom DIMM support to the Memory format parameter description in the Group: Memory / Topology table, and added description of the Fine granularity refresh parameter to the Mode Register Settings table.
    • In the Single Rank x8 Discrete (Component) Topology and Single Rank x16 Discrete (Component) Topology topics in the Board Design Guidelines section, added mention of the alert_n pin requiring an external pull-up resistor of approximately 10KΩ.
    • In the Intel® Agilex™ EMIF Pin Swapping Guidelines topic, expanded the note discussing the pin swapping rules enforced by the Intel® Quartus® Prime software.
  • In the QDR-IV chapter, removed the Core Clock Network section from the Resource Sharing Guidelines (Multiple Interfaces) topic.
Document Version Intel® Quartus® Prime Version IP Version Changes
2021.10.04 21.3 2.5.0
  • In the Architecture chapter:
    • Modified captions on existing figures in the I/O Bank topic, and added four additional figures.
    • Modified the two tables in the Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme topic.
  • In the Simulating chapter, changed Mentor Graphics to Siemens EDA, and ModelSim - Intel FPGA Edition to Questa - Intel FPGA Edition.
  • In the DDR4 chapter:
    • Modified the Example Designs with Multi-IPs table in the Intel Agilex EMIF IP DDR4 Parameters: Example Designs topic.
    • Added Register Map IP-XACT Support for Intel Agilex EMIF DDR4 IP topic.
    • Added a note to step 9 in the General Guidelines topic in the Pin Guidelines section.
    • In the Skew Matching Guidelines for DIMM Configurations topic, added two rows to the table.
    • In the Skew Matching Guidelines for DDR4 Discrete Configurations topic, added two rows to the table.
  • In the Controller Optimization chapter, added the Controller Pre-pay and Post-pay Refresh (DDR4 Only) topic.
  • In the Debugging chapter:
    • Updated the table in the Configuration and Status Registers topic.
    • Updated the Address Pattern topic.
    • Updated the Address Pattern topic and added several new topics:
      • Address Generator Modes
      • Address Generator MSB Indices
      • Address Generator Effective Width
      • Address Generator Relative Frequencies
      • Address Pattern Examples - Basic Mode
      • Address Pattern Examples - Advanced Mode
    • Updated the table in the Traffic Generator Status topic.
    • In the Configuring the Traffic Generator topic, updated the Configurations Tab figure, and added several new figures.
2021.07.09 21.2 2.4.2 In the Debugging chapter, modified the Code Value column in the Error Codes table in the Traffic Generator Status topic.
2021.06.21 21.2 2.4.2
  • In the Architecture chapter,
    • Added the Calibration Algorithms section.
    • Added information to the ECC Support description in the table in the Hard Memory Controller Features topic.
    • Added information to the ECC Controller description in the table in the Hard Memory Controller Main Control Path topic.
  • In the Simulation chapter, added information to the Skip Calibration Mode description in the Calibration Modes topic.
  • In the Debugging chapter:
    • Added Guidelines for Debugging Calibration Issues to the Using the EMIF Debug Toolkit section.
    • Added descriptions of the TG_VERSION and TG_START registers to the table in the Configuration and Status Registers topic.
    • Modified a sentence in the User Traffic section of the Starting Traffic with the Traffic Generator topic.
    • Added the Examples of Configuring the TG2 Traffic Generator topic.
2021.03.29 21.1 2.4.0
  • In the End-User Signals chapter, removed references to Ping-Pong PHY from the port descriptions in the Interface: ctrl_ecc_status table.
  • In the Product Architecture chapter:
    • In the I/O Bank topic, added I/O chaining diagrams for R29A, R31B, and R31C package devices.
    • In the Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme topic, added three rows to the DDRx72 EMIF With AVST and Address/Command Scheme with 4 I/O Lanes table.
  • In the DDR4 chapter, removed a redundant paragraph from the Data, Data Strobes, DM/DBI, and Optional ECC Signals topic.
  • In the Debugging chapter:
    • In Table 154. Configuration and Status Registers, modified the TG_CLEAR register description, and added three additional rows at the bottom of the table.
    • In Table 156. Error Codes, added an additional row to the bottom of the table, for the ERR_BURSTLENGTH_OVERFLOW_ON_FIRST_WRITE code name.
    • In the Traffic Generator Status Report topic:
      • Replaced the figure TG Status Report (Passing Traffic Pattern).
      • Replaced the figure TG Status Report (Failing Traffic Pattern).
      • Replaced the figure TG Status Report (While Running Infinite Traffic).
      • Added the figure TG Status Report (Attempt to Overflow Address Space).
    • In the Control and Status Registers table, changed the register name for the 0x40 entry.
2021.01.20 20.4 2.3.0
  • In the DDR4 chapter, added the Group: Example Designs / Example Design with Multi-IPs table to the Intel Agilex EMIF IP DDR4 Parameters: Example Designs topic.
2020.12.14 20.4 2.3.0
  • In the Product Architecture chapter, recast the text around the table in the Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme topic.
  • In the End-User Signals chapter, removed the AFI Signals and AFI 4.0 Timing Diagrams sections.
  • In the DDR4 chapter:
    • Modified the x4 DIMM Implementation topic.
    • Modified the ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and R Rank x 16 Discrete (Component) Topologies topic.
  • In the Debugging chapter:
    • Replaced the Adding Interfaces to a Design Example topic with Creating a Design Example with Multiple EMIF Interfaces.
    • Replaced the Using the Traffic Generator with the Generated Design Example topic with the Using the Default Traffic Generator section.
    • Retitled the Configurable Traffic Generator (TG2) section to Using the Configurable Traffic Generator (TG2).
2020.10.05 20.3 2.3.0
  • In the About chapter, updated the Release Information topic.
  • In the Product Architecture chapter, added device packages to the I/O Bank topic, and expanded the table in the Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme topic.
  • In the MMR Tables section of the End-User Signals chapter, added ECC error information to the ecc6: Address of Most Recent Correction Command Dropped topic.
  • In the Timing Closure chapter, made a minor addition to the first sentence.
  • Added the Intel® Agilex™ FPGA EMIF IP – Timing Closure chapter.
  • In the Debugging chapter, made changes to the following:
    • In the Debugging with the External Memory Interface Debug Toolkit section, made changes to the following topics:
      • Rerunning the Traffic Generator (added information on changing address ordering)
      • Calibration Report Tab
      • Calibrate Termination Tab (recast text and added image)
      • ISSPs Tab (added row to bottom of table)
      • Viewing Reports Graphically in the Eye Viewer (added an additional eye diagram)
    • In the Configurable Traffic Generator (TG2) Description section, made changes to the following topics:
      • Enabling the Traffic Generator in a Design Example
      • Configuration and Status Registers (changed description of TG_TEST_BYTEEN register)
      • Configuring the Traffic Generator (updated images)
      • Traffic Generator Preset Selection (new topic)
      • Traffic Generator Status Report (updated images)
    • In the On-Chip Debug Port section, made changes to the following topics:
      • I/O SSM calbus Bridge Data Structures and Usage (added note and figure, modified DQS Tree Structure table)
      • Parameter Table Arrays (modified 2 (DQS_C) entry in Example table)
      • Debug Data Structures (modified cur_interface_idx entry in the mem_summary_report table, and corrected text in debug_cal_data_struct section.
      • Example: Reading Calibration Results and Margins with the On-Chip Debug Port
    • In the Efficiency Monitor section, made changes to the following topics:
      • Enabling the Efficiency Monitor in a Design Example (updated second bullet and image)
      • Control and Status Registers (updated last row in table)
      • Opening the Efficiency Monitor Toolkit (updated images)
2020.06.22 20.2 2.2.0
  • In the Product Architecture chapter, made minor changes to the Intel® Agilex™ Calibration Stages and Intel® Agilex™ Calibration Algorithms topics.
  • In the Functional Simulation chapter, added text and a figure to the Simulation Walkthrough topic.
  • In the Debugging chapter, updated images throughout the Debugging with the External Memory Interface Debug Toolkit section.
  • In the Debugging chapter, made several changes to the Configurable Traffic Generator (TG2) section:
    • Minor change to terminology in the Default Traffic Pattern, Configuration and Status Registers, Test Duration / Instruction Pattern, and Address Pattern topics.
    • Expanded content in the Starting Traffic with the Traffic Generator topic.
    • Updated images in the Configuring the Traffic Generator and Traffic Generator Status Report topics.
  • In the Debugging chapter, added the EMIF On-chip Debug Port section.
2020.04.27 20.1 2.1.0
  • In the DDR4 chapter, modified guidelines 2 and 3, and added guideline 11, in the General Guidelines topic.
  • In the QDR-IV chapter:
    • Modified guidelines 2 and 3, and added guideline 11, in the General Guidelines topic.
    • Added guideline 4 to the I/O Bank section of the Resource Sharing Guidelines (Multiple Interfaces) topic.
2020.04.13 20.1 2.1.0
  • In the Introduction chapter:
    • Added QDR-IV support to the Intel® Agilex™ EMIF IP Protocol and Feature Support topic.
    • Added links to QDR-IV Parameter Descriptions to the Intel® Agilex™ EMIF IP Design Checklist topic.
  • In the Architecture chapter:
    • Added QDR-IV support to the Introduction topic.
  • In the End-User Signals chapter:
    • Added QDR-IV interfaces and signals to the Interface and Signal Descriptions section.
    • In the AFI 4.0 Timing Diagrams section, removed Write data sequence with CRC.
    • Implemented changes to the ctrlcfg1, sbcfg1, and caltiming4 tables in the Memory Mapped Register (MMR) Tables section.
  • Added the Intel® Agilex™ FPGA EMIF IP – QDR-IV Support chapter.
  • In the Debugging chapter:
    • Implemented numerous changes to the Debugging with the External Memory Interface Debug Toolkit section.
    • Added the Configurable Traffic Generator (TG2) Description section.
2020.02.10 19.4 2.0.0
  • In the DDR4 chapter:
    • Added the x4 DIMM Implementation topic to the Pin and Resource Planning section.
    • Added the Clamshell Topology topic to the DDR4 Board Design Guidelines section.
  • In the Debugging chapter, modified the last sentence of the Intermittent Issue Evaluation topic.
2019.12.16 19.4 2.0.0
  • In the Architecture chapter:
    • Modified the first sentence following Figure 7 in the I/O Bank topic.
    • Added the Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme topic.
  • In the DDR4 chapter:
    • Expanded the DDR4 Board Design Guidelines section.
  • In the Debugging chapter:
    • Added the Debugging With the External Memory Interface Debug Toolkit section.
  • Added External Memory Interfaces Intel® Agilex™ FPGA IP User Guide Archives topic.
2019.10.18 19.3  
  • In the Introduction chapter, revised the EMIF IP Design Flow flowchart.
  • In the Product Architecture chapter:
    • Updated the Intel Agilex I/O Subsystem figure in the EMIF Architecture: I/O Subsystem topic.
    • Modified the first paragraph, and updated the connectivity diagrams in the EMIF Architecture: I/O SSM topic.
    • Modified the Pin Index Mapping table in the EMIF Architecture: I/O Lane topic.
    • Added an explanation of Quasi-1T to the description of the Arbiter component in the Main Control Path Components table in the Hard Memory Controller Main Control Path topic.
    • Removed the note from the beginning of the Intel® Agilex™ EMIF for Hard Processor Subsystem topic.
  • In the DDR4 Support chapter:
    • Removed the Board Skew Equations section.
    • Modified entries for the Clock pin in the UDIMM, RDIMM, and LRDIMM Pin Options for DDR4 table.
    • Removed the Channel Signal Integrity Measurement and Package Deskew sections.
  • In the Timing Closure chapter:
    • Modified the Core to periphery (C2P) and Periphery to core (P2C) descriptions in the Timing Closure topic.
    • Removed references to Early I/O Timing Estimation.
  • In the Controller Optimization chapter:
    • In the Bank Interleaving topic, modified the names of the three supported interleaving options.
    • Added content to the paragraph introducing the examples, in the Using Auto-precharge to Achieve Highest Memory Bandwidth for DDR4 Interfaces topic.
  • In the Debugging chapter:
    • Added the Debugging with the External Memory Interface Debug Toolkit section.
    • Added the Using the Traffic Generator with the Generated Design Example topic.
2019.07.31 19.2 1.2.0
  • Added the About the External Memory Interfaces Intel® Agilex™ FPGA IP chapter.
  • In the topic Intel® Agilex™ EMIF for Hard Processor Subsystem, in the Product Architecture chapter, changed the description of Memory format in the table from 16GB support to 32GB support.
  • In the Intel® Agilex™ FPGA EMIF IP — End-User Signals chapter:
    • Removed emif_usr_reset_n_sec and emif_usr_clk_sec from Table 10, Interfaces for DDR4.
    • In the topic 3.1.1.10, mem for DDR4, modified the description of mem_a in the table.
    • Removed the 3.1.1.18 emif_usr_reset_n_sec for DDR4 and 3.1.1.19 emif_usr_clk_sec for DDR4 topics.
    • Removed sbcfg1, sideband2, sideband3, sideband5, sideband8, sideband10, and sideband15 from the Intel® Agilex™ EMIF IP Memory Mapped Register (MMR) Tables.
    • Changed the Bit High value for the second row in the dramtiming0 MMR table.
    • Changed the Field name and Description text for the fourth row in the caltiming4 MMR table.
    • Made several changes in the Description column of the sideband13 MMR table.
    • Changed the Field, Bit High, Bit Low, and Description values in the sideband14 MMR table.
  • In the Intel® Agilex™ EMIF IP DDR4 Parameters: Memory topic of the DDR4 chapter:
    • Removed the Enable ALERT#/PAR pins parameter and recast the description of the ALERT# pin placement parameter in the Group: Memory / Topology table.
  • In the Intel® Agilex™ EMIF IP DDR4 Parameters: Mem I/O topic, revised the description for the SPD Byte 145-147 - DB MDQ Drive Strength and RTT parameter.
  • In the Intel® Agilex™ EMIF IP DDR4 Parameters: Diagnostics topic:
    • Added the Group: Diagnostics / Example Design table.
    • Added the Group: Diagnostics / Traffic Generator table (marked as future support).
    • Added the Group: Diagnostics / Performance and Group: Diagnostics / Miscellaneous tables.
  • Added the Intel® Agilex™ EMIF IP DDR4 Parameters: Example Designs topic.
  • In the Intel® Agilex™ FPGA EMIF IP — Timing Closure chapter, revised the Optimizing Timing topic.
  • Removed occurrences of Ping Pong PHY throughout.
2019.04.02 19.1  
  • Initial release.

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