External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.4. Intel Agilex EMIF IP DDR4 Parameters: FPGA I/O

You should use Hyperlynx* or similar simulators to determine the best settings for your board. Refer to the EMIF Simulation Guidance wiki page for additional information.
Table 80.  Group: FPGA I/O / FPGA I/O Settings
Display Name Description
Voltage The voltage level for the I/O pins driving the signals between the memory device and the FPGA memory interface. (Identifier: PHY_DDR4_IO_VOLTAGE)
Use default I/O settings Specifies that a legal set of I/O settings are automatically selected. The default I/O settings are not necessarily optimized for a specific board. To achieve optimal signal integrity, perform I/O simulations with IBIS models and enter the I/O settings manually, based on simulation results. (Identifier: PHY_DDR4_DEFAULT_IO)
Table 81.  Group: FPGA I/O / FPGA I/O Settings / Address/Command
Display Name Description
I/O standard Specifies the I/O electrical standard for the address/command pins of the memory interface. The selected I/O standard configures the circuit within the I/O buffer to match the industry standard. (Identifier: PHY_DDR4_USER_AC_IO_STD_ENUM)
Output mode This parameter allows you to change the current drive strength or termination settings for the selected I/O standard. Perform board simulation with IBIS models to determine the best settings for your design. (Identifier: PHY_DDR4_USER_AC_MODE_ENUM)
Slew rate Specifies the slew rate of the memory bus data output pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the data output slew rate that provides the best eye opening for the data bus pins measured at the memory receiver. (Identifier: PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM)
Deemphasis mode Specifies the deemphasis mode of the address/command output pins. The deemphasis mode controls how quickly individual driver stages of the output buffer are enabled. Adjusting this setting can help control voltage overshoot at the receiver. Perform board simulations to determine the deemphasis setting that provides the best eye opening for the address and command signals. (Identifier: PHY_DDR4_USER_AC_DEEMPHASIS_ENUM)
Table 82.  Group: FPGA I/O / FPGA I/O Settings / Memory Clock
Display Name Description
I/O standard Specifies the I/O electrical standard for the memory clock pins. The selected I/O standard configures the circuit within the I/O buffer to match the industry standard. (Identifier: PHY_DDR4_USER_CK_IO_STD_ENUM)
Output mode This parameter allows you to change the current drive strength or termination settings for the selected I/O standard. Perform board simulation with IBIS models to determine the best settings for your design. (Identifier: PHY_DDR4_USER_CK_MODE_ENUM)
Slew rate Specifies the slew rate of the memory bus data output pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the data output slew rate that provides the best eye opening for the data bus pins measured at the memory receiver. (Identifier: PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM)
Deemphasis mode Specifies the deemphasis mode for the memory clock pins. The deemphasis mode controls how quickly individual driver stages of the output buffer are enabled. Adjusting this setting can help control voltage overshoot at the receiver. Perform board simulations to determine the deemphasis setting that provides the best eye opening for the memory clock signals. (Identifier: PHY_DDR4_USER_CK_DEEMPHASIS_ENUM)
Table 83.  Group: FPGA I/O / FPGA I/O Settings / Data Bus
Display Name Description
I/O standard Specifies the I/O electrical standard for the data and data clock/strobe pins of the memory interface. The selected I/O standard option configures the circuit within the I/O buffer to match the industry standard. (Identifier: PHY_DDR4_USER_DATA_IO_STD_ENUM)
Output mode This parameter allows you to change the output current drive strength or termination settings for the selected I/O standard. Perform board simulation with IBIS models to determine the best settings for your design. (Identifier: PHY_DDR4_USER_DATA_OUT_MODE_ENUM)
Slew rate Specifies the slew rate of the memory bus data output pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the data output slew rate that provides the best eye opening for the data bus pins measured at the memory receiver. (Identifier: PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM)
Deemphasis mode Specifies the deemphasis mode for the memory bus data output pins. The deemphasis mode controls how quickly individual driver stages of the output buffer are enabled. Adjusting this setting can help control voltage overshoot at the receiver. Perform board simulations to determine the deemphasis setting that provides the best eye opening for the data bus pins measured at the memory receiver. (Identifier: PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM)
Input mode This parameter allows you to change the input termination settings for the selected I/O standard. Perform board simulation with IBIS models to determine the best settings for your design. (Identifier: PHY_DDR4_USER_DATA_IN_MODE_ENUM)
Use recommended initial Vrefin Specifies that the initial Vrefin setting is calculated automatically, to a reasonable value based on termination settings. (Identifier: PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN)
Initial Vrefin Specifies the initial value for the reference voltage on the data pins(Vrefin). This value is entered as a percentage of the supply voltage level on the I/O pins. The specified value serves as a starting point and may be overridden by calibration to provide better timing margins. If you choose to skip Vref calibration (Diagnostics tab), this is the value that is used as the Vref for the interface. (Identifier: PHY_DDR4_USER_STARTING_VREFIN)
Table 84.  Group: FPGA I/O / FPGA I/O Settings / PHY Inputs
Display Name Description
PLL reference clock I/O standard Specifies the I/O standard for the PLL reference clock of the memory interface. (Identifier: PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM)
RZQ I/O standard Specifies the I/O standard for the RZQ pin used in the memory interface. (Identifier: PHY_DDR4_USER_RZQ_IO_STD_ENUM)

Did you find the information on this page useful?

Characters remaining:

Feedback Message