External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.2.3. pll_ref_clk for QDR-IV

PLL reference clock input
Table 42.  Interface: pll_ref_clkInterface type: Clock Input
Port Name Direction Description
pll_ref_clk Input PLL reference clock input