External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.11. dramaddrw

address=42(32 bit)

Field Bit High Bit Low Description Access
cfg_col_addr_width 4 0 The number of column address bits for the memory devices in your memory interface. Read
cfg_row_addr_width 9 5 The number of row address bits for the memory devices in your memory interface. Read
cfg_bank_addr_width 13 10 The number of bank address bits for the memory devices in your memory interface. Read
cfg_bank_group_addr_width 15 14 The number of bank group address bits for the memory devices in your memory interface. Read
cfg_cs_addr_width 18 16 The number of chip select address bits for the memory devices in your memory interface. Read

Did you find the information on this page useful?

Characters remaining:

Feedback Message