External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022

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5.3.3. Editing the Simulation Design Example with the Platform Designer

  1. Open the synthesizable design example by clicking Open Project, and then selecting ed_synth.qpf in the <example_project>/qii folder:
    Figure 100. Opening ed_synth.qpf
  2. After the project has loaded, open ed_sim.qsys in the <example_design_path>/sim folder:
    Figure 101. Opening ed_sim.qsys
  3. In the Platform Designer, remove the Sim Checker and Traffic Generator:
    Figure 102. Making Changes in the Simulation Example Design
  4. Insert a Mentor Graphics AXI4 Master BFM (Intel FPGA Edition) to the simulation design example:
    1. In the IP Catalog, click Library > Basic Functions > Simulation; Debug and Verification > Mentor Graphic AXI4 Master BFM (Intel FPGA Edition).
      Figure 103. Inserting AXI4 master BFM
    2. Parameterize the AXI4 Master BFM using the values shown in the figure below; retain the other default settings.
      Figure 104. AXI Master BFM Settings
  5. Make the following connections on the AXI4 master BFM as illustrated in the following figure:
    1. mgc_axi_master_0.altera_axi_master to emif_fm_0.ctrl_amm_0
    2. mgc_axi_master_0.clock_sink to emif_fm_0.emif_usr_clk
    3. mgc_axi_master_0.reset_sink to emif_fm_0.emif_usr_reset_n (This connection is changed manually in ed_sim.v in a later stage, to keep the AXI4 Master BFM in reset until cal_success=1’b1 ).
      Figure 105. Connectivity between EMIF IP and AXI4 Master BFM

      You can ignore the following warning message after connecting the AXI Master BFM:

      ed_sim.emif_fm_0	emif_fm_0.oct must be exported or connected to a matching conduit as it has unconnected inputs.
  6. Save your edits and click Generate HDL.
  7. In the generation window:
    1. Select None for Create HDL design files for synthesis, because we are not generating a synthesizable design example.
    2. Select VCS to generate the simulation scripts for VCS simulator.
    3. Click Generate to generate the files.
    Figure 106. Settings for Generating Files

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