External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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3.1.5. Intel® Agilex™ EMIF Architecture: Input DQS Clock Tree

The input DQS clock tree is a balanced clock network that distributes the read capture clock (such as QK/QK# which are free-running read clocks) and strobe (such as DQS/DQS#) from the external memory device to the read capture registers inside the I/Os.

You can configure an input DQS clock tree in x4 mode, x8/x9 mode, or x18 mode.

Within every bank, only certain physical pins at specific locations can drive the input DQS clock trees. The pin locations that can drive the input DQS clock trees vary, depending on the size of the group.

Table 7.  Pins Usable as Read Capture Clock / Strobe Pair
Group Size Index of Lanes Spanned by Clock Tree 1 Sub-Bank Index of Pins Usable as Read Capture Clock / Strobe Pair
DQS p DQS n
x4 0A Bottom 4 5
x4 0B 6 7
x4 1A 16 17
x4 1B 18 19
x4 2A 28 29
x4 2B 30 31
x4 3A 40 41
x4 3B 42 43
x8 / x9 0 4 5
x8 / x9 1 16 17
x8 / x9 2 28 29
x8 / x9 3 40 41
x18 0, 1 4 5
x18 2, 3 28 29
x4 0A Top 52 53
x4 0B 54 55
x4 1A 64 65
x4 1B 66 67
x4 2A 76 77
x4 2B 78 79
x4 3A 88 89
x4 3B 90 91
x8 / x9 0 52 53
x8 / x9 1 64 65
x8 / x9 2 76 77
x8 / x9 3 88 89
x18 0,1 53 53
x18 2,3 76 77
Note: 1 A and B refer to the two nibbles within the lane.

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