External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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3.1.6. Intel® Agilex™ EMIF Architecture: PHY Clock Tree

Dedicated high-speed clock networks drive I/Os in Intel® Agilex™ EMIF. Each PHY clock network spans only one sub-bank.

The relatively short span of the PHY clock trees results in low jitter and low duty-cycle distortion, maximizing the data valid window.

The PHY clock tree in Intel® Agilex™ devices can run as fast as 1.6 GHz. All Intel® Agilex™ external memory interfaces use the PHY clock trees.

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