External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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4.1.1.3. pll_ref_clk for DDR4

PLL reference clock input
Table 16.  Interface: pll_ref_clkInterface type: Clock Input
Port Name Direction Description
pll_ref_clk Input PLL reference clock input

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