External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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6.1.7. Intel Agilex EMIF IP DDR4 Parameters: Diagnostics

Table 92.  Group: Diagnostics / Simulation Options
Display Name Description
Calibration mode Specifies whether to skip memory interface calibration during simulation, or to simulate the full calibration process.

Simulating the full calibration process can take hours (or even days), depending on the width and depth of the memory interface. You can achieve much faster simulation times by skipping the calibration process, but that is only expected to work when the memory model is ideal and the interconnect delays are zero.

If you enable this parameter, the interface still performs some memory initialization before starting normal operations. Abstract PHY is supported with skip calibration.

(Identifier: DIAG_DDR4_SIM_CAL_MODE_ENUM)
Table 93.  Group: Diagnostics / Calibration Debug Options
Display Name Description
Skip address/command parity check during calibration Allows you to skip the address/command parity check during calibration. This parity check comes from reading the alert0_n pin from the DDR4 interface. (Identifier: DIAG_DDR4_SKIP_AC_PARITY_CHECK)
Table 94.  Group: Diagnostics / Example Design
Display Name Description
Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port Specifies the connectivity of an Avalon slave interface for use by the Quartus Prime EMIF Debug Toolkit or user core logic.

If you set this parameter to "Disabled", no debug features are enabled. If you set this parameter to "Export", an Avalon slave interface named "cal_debug" is exported from the IP. To use this interface with the EMIF Debug Toolkit, you must instantiate and connect an EMIF debug interface IP core to it, or connect it to the cal_debug_out interface of another EMIF core. If you select "Add EMIF Debug Interface", an EMIF debug interface component containing a JTAG Avalon Master is connected to the debug port, allowing the core to be accessed by the EMIF Debug Toolkit.

Only one EMIF debug interface should be instantiated per I/O column. You can chain additional EMIF or PHYLite cores to the first by enabling the "Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option for all cores in the chain, and selecting "Export" for the "Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option on all cores after the first.

(Identifier: DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE)
Enable In-System-Sources-and-Probes Enables In-System-Sources-and-Probes in the example design for common debug signals, such as calibration status or example traffic generator per-bit status. This parameter must be enabled if you want to do driver margining using the EMIF Debug Toolkit. (Identifier: DIAG_DDR4_EX_DESIGN_ISSP_EN)
Table 95.  Group: Diagnostics / Traffic Generator (settings only applicable for example design)
Display Name Description
Use configurable Avalon traffic generator 2.0 This option allows you to add the new configurable Avalon traffic generator to the example design. (Identifier: DIAG_DDR4_USE_TG_AVL_2)
Enable default traffic pattern (pattern configured during compile-time) Specifies that the default traffic pattern is enabled. If this parameter is enabled, a default traffic pattern is run immediately every time the traffic generator comes out of reset. If this parameter is disabled, the traffic generator does not run any traffic until it is signaled to start by its Avalon configuration interface. (Identifier: DIAG_DDR4_ENABLE_DEFAULT_MODE)
Enable user-configured traffic pattern (pattern configured during run-time) Specifies that the user-defined traffic pattern is enabled. If this parameter is enabled, the traffic generator responds to the configuration interface and launch a user-configured traffic pattern when signaled to. If this parameter is disabled, the traffic generator ignores commands on the configuration interface, and does not run any user-defined traffic. (Identifier: DIAG_DDR4_ENABLE_USER_MODE)
TG2 default traffic duration This option allows adjusting the pattern length of default (compile-time) traffic (Identifier: DIAG_DDR4_TG2_TEST_DURATION)
TG2 Configuration Interface Mode Specifies the connectivity of an Avalon slave interface for use by the TG Configuration Toolkit or user core logic. If you set this parameter to "Export", an Avalon slave interface named "tg_cfg" is exported from the IP. If you select "JTAG", a JTAG Avalon Master Endpoint is connected to the configuration interface, allowing the core to be accessed by the TG Configuration Toolkit. (Identifier: DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE)
Table 96.  Group: Diagnostics / Performance
Display Name Description
Efficiency Monitor Mode Adds an Efficiency Monitor component to the Avalon-MM interface of the memory controller, allowing you to view efficiency statistics of the interface. You can access the efficiency statistics using the EMIF Efficiency Monitor Toolkit. (Identifier: DIAG_DDR4_EFFICIENCY_MONITOR)
Table 97.  Group: Diagnostics / Miscellaneous
Display Name Description
Export PLL lock signal Specifies whether to export the pll_locked signal at the IP top-level to indicate status of PLL. (Identifier: DIAG_EXPORT_PLL_LOCKED)
Export Address/Command parity error indicator Specifies whether to export the ac_parity_err interface at the IP top-level to indicate if a parity error was detected on the Address/Command bus by the memory, causing ALERT_N to toggle. (Identifier: DIAG_DDR4_AC_PARITY_ERR)

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