External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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11.9.4. Configuration and Status Registers

You can configure the user traffic pattern by writing to configuration registers that influence the resulting traffic pattern.

Configuration registers that govern the resulting traffic pattern affect one of the following aspects of the pattern:

  • Test duration / Instruction pattern
  • Address pattern
  • Data pattern
Note: This section describes the registers that configure a traffic pattern as seen on the ctrl_amm interface.

Configuration and Status Registers

Symbol Address Register Name Number of Registers Access Type Register Section Register Description
0x4 TG_START 1 Read/Write Start Perform a write to this register to start the traffic generator.
0x8 TG_LOOP_COUNT 1 Read/Write Test Duration/Instruction Pattern Number of read/write loops to be run. A loop is defined as one block of writes followed by a block of reads. Setting to 0 enables Infinite User Mode.
0xC TG_WRITE_COUNT 1 Read/Write Test Duration/Instruction Pattern Number of unique writes to be performed in each loop.
0x10 TG_READ_COUNT 1 Read/Write Test Duration/Instruction Pattern Number of unique reads to be performed in each loop.
0x14 TG_WRITE_REPEAT_COUNT 1 Read/Write Test Duration/Instruction Pattern Number of times to repeat each write operation (i.e. same address and same data).
0x18 TG_READ_REPEAT_COUNT 1 Read/Write Test Duration/Instruction Pattern Number of times to repeat each read operation (i.e. same address).
0x1C TG_BURST_LENGTH 1 Read/Write Test Duration/Instruction Pattern Avalon burst length.
0x20 TG_CLEAR 1 Read/Write Status

Clears the failure status registers. Allows clearing these registers independently from one another by writing a 1 to the following bits:

BIT0 - Clears the recorded PNF data and starts fresh.

BIT1 - Clears the recorded number of avalon reads.

BIT2 - Clears the recorded data of the first failure (address; expected data; actual data).

BIT3 - Clears the burstlength overflow flag and burstlength overflow address.

BIT4 - Clears the WORM mode failure info (i.e. targeted read data)

0x38 TG_RW_GEN_IDLE_COUNT 1 Read/Write Test Duration/Instruction Pattern Number of cycles for which TG remains idle between a write block and the next read block.
0x3C TG_RW_GEN_LOOP_IDLE_COUNT 1 Read/Write Test Duration/Instruction Pattern Number of cycles for which TG remains idle between a read block and the next write block.
0x40 TG_SEQ_START_ADDR_WR 6 Read/Write Address Pattern Start address for writes; used as seed address in Random Mode.
0x80 TG_ADDR_MODE_WR 6 Read/Write Address Pattern

Array that selects address generator mode for each address field for writes

TG_ADDR_MODE==0: Fixed

TG_ADDR_MODE==1: Random

TG_ADDR_MODE==2: Sequential

TG_ADDR_MODE==3 Field Unused.

0xC0 TG_RETURN_TO_START_ADDR 1 Read/Write Address Pattern Setting to 1 specifies to return to start address in each loop. Setting to 0 specified to resume the address pattern from where the previous loop left off.
0x100 TG_SEQ_ADDR_INCR 6 Read/Write Address Pattern Array of increments for fields 0-5 to be used for each address field when address is to be incremented sequentially. This value should be at least the value of TG_BURST_LENGTH for field 0.
0x140 TG_SEQ_START_ADDR_RD 6 Read/Write Address Pattern Start address for reads; used as seed address in Random Mode.
0x180 TG_ADDR_MODE_RD 6 Read/Write Address Pattern

Array that selects address generator mode for each address field for reads

TG_ADDR_MODE==0: Fixed

TG_ADDR_MODE==1: Random

TG_ADDR_MODE==2: Sequential

TG_ADDR_MODE==3 Field Unused.

0x1C0 TG_PASS 1 Read Only Status Reading a 1 indicates that the traffic generator passed at the end of all the test stages.
0x1C4 TG_FAIL 1 Read Only Status Reading a 1 indicates that the traffic generator failed at the end of all the test stages.
0x1C8 TG_FAIL_COUNT_L 1 Read Only Status Number of failed reads (lower 32 bits).
0x1CC TG_FAIL_COUNT_H 1 Read Only Status Number of failed reads (upper 32 bits).
0x1D0 TG_FIRST_FAIL_ADDR_L 1 Read Only Status Address of the first failed read (lower 32 bits).
0x1D4 TG_FIRST_FAIL_ADDR_H 1 Read Only Status Address of the first failed read (upper 32 bits).
0x1D8 TG_TOTAL_READ_COUNT_L 1 Read Only Status Number of read operations executed - sent and received (lower 32 bits).
0x1DC TG_TOTAL_READ_COUNT_H 1 Read Only Status Number of read operations executed - sent and received (upper 32 bits).
0x1E0 TG_TEST_COMPLETE 1 Read Only Status Reading a 1 indicates that the traffic generator run is complete.
0x1E4 TG_INVERT_BYTEEN 1 Read/Write Data/Byte-Enable Pattern Setting to 1 specifies to invert byte-enable values and writedata.
0x1E8 TG_RESTART_DEFAULT_TRAFFIC 1 Read/Write Data/Byte-Enable Pattern Perform a write to this register to restart the default mode.
0x1EC TG_USER_WORM_EN 1 Read/Write Data/Byte-Enable Pattern Setting to 1 enables WORM (Write Once Read Many) Mode. If a data mismatch is encountered in WORM mode TG2 stops at the first data mismatch and issues a second read to the same address.
0x1F0 TG_TEST_BYTEEN 1 Read/Write Data/Byte-Enable Pattern Perform a write to this register to indicate TG is in invert byte-enable testing mode.
0x1F4 TG_TIMEOUT 1 Read Only Status Reading a 1 indicates that the traffic generator timeout.
0x1F8 TG_NUM_DATA_GEN 1 Read Only Data/Byte-Enable Pattern Number of data generators.
0x1FC TG_NUM_BYTEEN_GEN 1 Read Only Data/Byte-Enable Pattern Number of byte enable generators.
0x200 TG_RDATA_WIDTH 1 Read Only Data/Byte-Enable Pattern Width of read data and PNF signals.
0x204 TG_ERROR_REPORT 1 Read Only Data/Byte-Enable Pattern Reports illegal configurations of TG2.
0x208 TG_DATA_RATE_WIDTH_RATIO 1 Read Only Data/Byte-Enable Pattern Data rate width ratio is the ratio between the data width at the ctrl_amm interface and the data width at the memory interface.
0x240 TG_PNF 18 Read Only Status Persistent PNF (Pass Not Fail) signal. Bus Width = TG_RDATA_WIDTH.
0x340 TG_FAIL_EXPECTED_DATA 1 Read Only Status Expected data on the first failure. Bus Width = TG_RDATA_WIDTH.
0x440 TG_FAIL_READ_DATA 1 Read Only Status Received data on the first failure. Bus Width = TG_RDATA_WIDTH.
0x540 TG_DATA_SEED TG_NUM_DATA_GEN Read/Write Data Generator Seed or starting value for each data generator (DG). This consists of TG_NUM_DATA_GEN entries.
0x580 TG_BYTEEN_SEED TG_NUM_BYTEEN_GEN Read/Write Data/Byte-Enable Pattern Seed or starting value for each byte-enable generator (BEG). This consists of TG_NUM_BYTEEN_GEN entries.
0x5C0 TG_PPPG_SEL TG_NUM_DATA_GEN Read/Write Data Generator Select from available pattern modes 0: Fixed; 1: PRBS7; 2: PRBS15; 3: PRBS31; 4: Rotating.
0x600 TG_BYTEEN_SEL TG_NUM_BYTEEN_GEN Read/Write Data/Byte-Enable Pattern Select from available pattern modes 0: Fixed; 1: PRBS7; 2: PRBS15; 3: PRBS31; 4: Rotating.
0x640 TG_ADDR_FIELD_RELATIVE_FREQ 6 Read/Write Address Pattern Array to set the frequency of each field. The value of the relative frequency is an integer that specifies after how many unique address commands the field updates.
0x680 TG_ADDR_FIELD_MSB_INDEX 5 Read/Write Address Pattern Array to set the MSB position of fields 0-4. Field 5 is redundant and does not need to be specified. MSB position implies the field width.
0x6C0 TG_BURSTLENGTH_OVERFLOW_OCCURRED 1 Read Only Status Reading a 1 indicates that an attempt was made to write outside of the address space. This occurrs when the current address plus the burstlength is greater than the total address space.
0x700 TG_BURSTLENGTH_FAIL_ADDR_L 1 Read Only Status Indicates the address where an address overflow occurred due to burstlength being greater than the difference between the write/read address and the last memory address (lower 32 bits).
0x704 TG_BURSTLENGTH_FAIL_ADDR_H 1 Read Only Status Indicates the address where an address overflow occurred due to burstlength being greater than the difference between the write/read address and the last memory address (lower 32 bits).
0x740 TG_WORM_MODE_TARGETTED_DATA 1 Read Only Status Received data from the targeted read. Targeted read data is set when WORM mode is enabled and the result of the second read to the first fail address occurs.

In the table above, some configuration settings and status information can fit within one 32-bit register, while others are broken into several registers. The Starting Address column indicates the address of the first register in the set while the Number of Registers column indicates the number of registers located after the start address.

For example: TG_PPPG_SEL occupies 8 registers when TG_NUM_DATA_GEN=8, so the data can be accessed by reading from addresses 0x5C0, 0x5C4, … 0x5E0.

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