External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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6.1.2. Intel Agilex EMIF IP DDR4 Parameters: Memory

Table 74.  Group: Memory / Topology
Display Name Description
Memory format Specifies the format of the external memory device. The following formats are supported: Component - a Discrete memory device; UDIMM - Unregistered/Unbuffered DIMM where address/control, clock, and data are unbuffered; RDIMM - Registered DIMM where address/control and clock are buffered; LRDIMM - Load Reduction DIMM where address/control, clock, and data are buffered. LRDIMM reduces the load to increase memory speed and supports higher densities than RDIMM; SODIMM - Small Outline DIMM is similar to UDIMM but smaller in size and is typically used for systems with limited space. Some memory protocols may not be available in all formats. (Identifier: MEM_DDR4_FORMAT_ENUM)
Note:
  1. Intel® Agilex™ devices do not support custom DIMMs,
  2. Intel does not provide support for customer-built custom DIMMs.
  3. Intel does not provide support for memory down where components are laid out with a registered clock driver (RCD) chip for clock/address/command buffering or data buffering.
  4. Intel continues to provide support for off-the-shelf JEDEC-compliant DIMMs, and memory down without RCD or data buffering, as well as clamshell topology, supported subject to Intel board design guidelines.
DQ width Specifies the total number of data pins in the interface. (Identifier: MEM_DDR4_DQ_WIDTH)
DQ pins per DQS group Specifies the total number of DQ pins per DQS group. (Identifier: MEM_DDR4_DQ_PER_DQS)
Number of DQS groups Specifies the number of DQS groups in the interface. This value is automatically calculated as the DQ width divided by the number of DQ pins per DQ group.
Number of clocks Specifies the number of CK/CK# clock pairs exposed by the memory interface. Usually more than 1 pair is required for RDIMM/LRDIMM formats. The value of this parameter depends on the memory device selected; refer to the data sheet for your memory device. (Identifier: MEM_DDR4_CK_WIDTH)
Number of DIMMs Total number of DIMMs. (Identifier: MEM_DDR4_NUM_OF_DIMMS)
Number of physical ranks per DIMM Number of ranks per DIMM. For LRDIMM, this represents the number of physical ranks on the DIMM behind the memory buffer (Identifier: MEM_DDR4_RANKS_PER_DIMM)
Number of chip selects per DIMM Specifies the number of chip selects per DIMM.
Number of Chip Select Specifies the number of chip select.
Chip ID width Specifies the number of chip ID pins. Only applicable to registered and load-reduced DIMMs that use 3DS/TSV memory devices. (Identifier: MEM_DDR4_CHIP_ID_WIDTH)
Row address width Specifies the number of row address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of address pins needed for access to all available rows. (Identifier: MEM_DDR4_ROW_ADDR_WIDTH)
Column address width Specifies the number of column address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of address pins needed for access to all available columns. (Identifier: MEM_DDR4_COL_ADDR_WIDTH)
Bank address width Specifies the number of bank address pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of bank address pins needed for access to all available banks. (Identifier: MEM_DDR4_BANK_ADDR_WIDTH)
Bank group width Specifies the number of bank group pins. Refer to the data sheet for your memory device. The density of the selected memory device determines the number of bank group pins needed for access to all available bank groups. (Identifier: MEM_DDR4_BANK_GROUP_WIDTH)
Data mask Indicates whether the interface uses data mask (DM) pins. This feature allows specified portions of the data bus to be written to memory (not available in x4 mode). One DM pin exists per DQS group. (Identifier: MEM_DDR4_DM_EN)
Write DBI Indicates whether the interface uses write data bus inversion (DBI). This feature provides better signal integrity and write margin. This feature is unavailable if Data Mask is enabled or in x4 mode. (Identifier: MEM_DDR4_WRITE_DBI)
Read DBI Specifies whether the interface uses read data bus inversion (DBI). Enable this feature for better signal integrity and read margin. This feature is not available in x4 configurations. (Identifier: MEM_DDR4_READ_DBI)
Enable address mirroring for odd chip-selects Enabling address mirroring for multi-CS discrete components. Typically used when components are arranged in a clamshell layout. (Identifier: MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN)
Enable address mirroring for odd ranks Enabling address mirroring for dual-rank or quad-rank DIMM. (Identifier: MEM_DDR4_MIRROR_ADDRESSING_EN)
ALERT# pin placement Specifies placement for the mem_alert_n signal. If you select "Automatically select a location", the IP automatically selects a pin for the mem_alert_n signal. If you select this option, no additional location constraints can be applied to the mem_alert_n pin, or a fitter error results during compilation. For devices in the Agilex Family: You have the option of manually selecting either Address/Command Lane 2, Pin 8 or Address/Command Lane 3, Pin 8 only. For interfaces containing multiple memory devices, you should connect the ALERT# pins together to the ALERT# pin on the FPGA. (Identifier: MEM_DDR4_ALERT_N_PLACEMENT_ENUM)
Table 75.  Group: Memory / Latency and Burst
Display Name Description
Memory CAS latency setting Specifies the number of clock cycles between the read command and the availability of the first bit of output data at the memory device. Overall read latency equals the additive latency (AL) + the CAS latency (CL). Overall read latency depends on the memory device selected; refer to the datasheet for your device. (Identifier: MEM_DDR4_TCL)
Memory write CAS latency setting Specifies the number of clock cycles from the release of internal write to the latching of the first data in at the memory device. This value depends on the memory device selected; refer to the datasheet for your device. (Identifier: MEM_DDR4_WTCL)
Memory additive CAS latency setting Determines the posted CAS additive latency of the memory device. Enable this feature to improve command and bus efficiency, and increase system bandwidth. (Identifier: MEM_DDR4_ATCL_ENUM)
Table 76.  Group: Memory / Mode Register Settings
   
Addr/CMD parity latency Additional latency incurred by enabling address/command parity check after calibration. Select a value to enable address/command parity with the latency associated with the selected value. Select Disable to disable address/command parity. Address/command parity is enabled automatically during calibration regardless of the value of this setting.
Fine granularity refresh Increased frequency of refresh in exchange for shorter refresh. Shorter tRFC and increased cycle time can produce higher bandwidth. (Identifier: MEM_DDR4_FINE_Granularity_Refresh)

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