External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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11.10.3. I/O SSM User-RAM Data Structures and Usage

The I/O SSM User-Ram spans addresses in the range: 0x0500_0000 – 0x0500_0fff, where each address represents a 32-bit word.

At the base address of the user-ram, is the Global Parameter Table , which contains pointers to the per-interface parameter table. The per-interface parameter table contains a pointer to the Debug Data Structure. There is one debug data structure per emif_cal IP (that is, one per I/O row).

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